K
Keith R. Williams
Guest
In article <uR8Sb.2538$CJ1.223@lakeread01>, tim@prolectron.com says...
Hfe, Vce(sat), and Vbe(sat) are specified with a 300uS pulse at 2% duty
cycle. Exceed these limits and all bets are off (including package
integrity ;-).
Now the Vce(sat) spec calls for 3A Ic with Ib=.375A and is 1.2V. I
*assume* this goes with the Vbe(sat) of 1.8V at IC=3A (consistent so
far). So you have 1.8V Vbe and 1.2V Vce, so the base-collector
junction is forward biased by .6V. Ok, that's saturation. Don't do
this for more than 300uS though. The magic smoke is near!
What I don't understand is the Vbe(sat) condition of Vce=4V (it was
1.2V with this collector current in the line above). The transistor is
*not* in saturation with Vce=4V and Vbe=1.8V (Base-collector junction
is reverse biased by 2.2V).
Other comments?
--
Keith
Strange! First of all, look at the footnote for these three specs."Keith R. Williams" <krw@attglobal.net> wrote in message news:MPG.1a82d878c8e3fe70989b96@enews.newsguy.com...
In article <Q0WRb.2397$CJ1.2071@lakeread01>, tim@prolectron.com says...
"Keith R. Williams" <krw@attglobal.net> wrote in message news:MPG.1a81ea41f1329e42989b94@enews.newsguy.com...
In article <kTURb.2382$CJ1.347@lakeread01>, tim@prolectron.com says...
"Jon" <na@na.com> wrote in message news:m0TRb.28982$6O4.763108@bgtnsc04-news.ops.worldnet.att.net...
Thanks for the link, Tim. I had pulled down a similar datasheet, but I
guess that I'm just not yet too comfortable reading these things. I cannot
believe that the current gain is over 100. That is pretty remarkable.
These are pretty sensitive little switches!
If I have a maximum current gain of 100, what would happen if I tried to
pass a current that is 200 times greater than the base current? Would the
transistor simply limit it to 100 times? For example, let's say I'm
supplying 10mA to the base, but I try to pass 200ma through the
collector-emitter. Would the transistor simply limit the current to the
value on the DC current gain chart?
Yes.
The datasheet shows a maximum Vebo of 5V for this transistor. I read that
that is the break-down voltage between the base and the emitter, but I'm not
too clear on what that means. I also see that the base-emitter saturation
voltage is 1.8V max, and I'm not too clear on that, either.
That means you can put 5 volts more than the emitter into the base. It would be in serious saturation at that point.
No, BVebo is the breakdown voltage from the emitter to the base (with
the collector open) with the junction *reverse* biased. In an NPN this
would mean the maximum voltage base can be driven *below* the emitter.
If you drive the base voltage 5V *above* the emitter, you'll let out
the magic smoke. ;-)
You are correct. Base voltage below the emitter.
The saturation voltage, as I recall, is the base-emitter voltage at which the transistor junction is saturated at its max
collector-emitter current rating. Please correct me if I am wrong.
No, a transistor is in saturation when its base-collector junction is
forward biased. The saturation voltage is then the voltage from
collector to emitter, which will be lower than the base-emitter
(I.e. < ~.7V, typically <.4V), since both junctions are forward biased.
--
Keith
What I was refering to was the phrase "base-emitter saturation voltage". I should have been more specific. Are you familiar with
that rating?
Nope, I'm not familliar with that rating. Can you point me to a spec
sheet or some context where this is used?
--
Keith
I would be happy to do that for ya !^)
http://www.fairchildsemi.com/ds/TI/TIP31.pdf
Check under "Electrical Characteristics" near the bottom.
Hfe, Vce(sat), and Vbe(sat) are specified with a 300uS pulse at 2% duty
cycle. Exceed these limits and all bets are off (including package
integrity ;-).
Now the Vce(sat) spec calls for 3A Ic with Ib=.375A and is 1.2V. I
*assume* this goes with the Vbe(sat) of 1.8V at IC=3A (consistent so
far). So you have 1.8V Vbe and 1.2V Vce, so the base-collector
junction is forward biased by .6V. Ok, that's saturation. Don't do
this for more than 300uS though. The magic smoke is near!
What I don't understand is the Vbe(sat) condition of Vce=4V (it was
1.2V with this collector current in the line above). The transistor is
*not* in saturation with Vce=4V and Vbe=1.8V (Base-collector junction
is reverse biased by 2.2V).
Other comments?
--
Keith