timing issues at high speed

[Jon Elson]

I have an interface project using XC9500XL CPLDs, using iSE 10.1,
and it grounds all pins that don't have logic connected to them.
I have a couple pins connected to external busses, so they do not
need to be held to prevent floating voltages. I see in the pin report
that they have been grounded with the "PGND" setting. Is there a way in
the UCF file or other way to prevent these several pins from getting the
PGND option? I'd want other unused pins to still be treated that way,
but these pins are wired on the board for future expansion, but are
now jamming bus signals.

Thanks,

Jon

 

[Mike Treseler]

On 2/23/2011 1:09 AM, salimbaba wrote:

All the inputs are synchronized with the state machine clock. It has
something to do with metastability of the signal that starts the state
machine because when i removed it, everything was in place. State machine
was in the IDLE mode as it should be.

That start signal is also an input.
Is it synchronized?

-- Mike Treseler

 

[salimbaba]

On 2/23/2011 1:09 AM, salimbaba wrote:

All the inputs are synchronized with the state machine clock. It has
something to do with metastability of the signal that starts the state
machine because when i removed it, everything was in place. Stat
machine
was in the IDLE mode as it should be.

That start signal is also an input.
Is it synchronized?

-- Mike Treseler


Yes it is synchronized. Ok i have solved the problem, in my opinion it mus

be something to do with metastability of the start signal. I have solved i
by ANDing the start signal with a sync signal which i generate after 5
clock cycles. So, it ensures that no glitches or anything like that passe
through and my state machines don't get triggered. Don't know if it's
good thing to do but what ever floats the boat, right ? Also, if there's
better way around lemme know.And also, if anyone knows why this i
happening other than what i think, kindly tell me that also.


thanks

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[RCIngham]

On 2/23/2011 1:09 AM, salimbaba wrote:

All the inputs are synchronized with the state machine clock. It has
something to do with metastability of the signal that starts the state
machine because when i removed it, everything was in place. State
machine
was in the IDLE mode as it should be.

That start signal is also an input.
Is it synchronized?

-- Mike Treseler


Yes it is synchronized. Ok i have solved the problem, in my opinion i
must
be something to do with metastability of the start signal. I have solve
it
by ANDing the start signal with a sync signal which i generate after 50
clock cycles. So, it ensures that no glitches or anything like tha
passes
through and my state machines don't get triggered. Don't know if it's a
good thing to do but what ever floats the boat, right ? Also, if there'
a
better way around lemme know.And also, if anyone knows why this is
happening other than what i think, kindly tell me that also.


thanks

Metastability is a random event. Its effects won't be consistent from on
test to another. Delaying the ->Starting transition in your FSM might b
the right solution to the wrong problem.


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[Bob Perlman]

On Feb 23, 10:16 pm, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:

On 2/23/2011 1:09 AM, salimbaba wrote:

All the inputs are synchronized with the state machine clock. It has
something to do with metastability of the signal that starts the state
machine because when i removed it, everything was in place. State
machine
was in the IDLE mode as it should be.  

That start signal is also an input.
Is it synchronized?

                -- Mike Treseler

Yes it is synchronized. Ok i have solved the problem, in my opinion it must
be something to do with metastability of the start signal. I have solved it
by ANDing the start signal with a sync signal which i generate after 50
clock cycles. So, it ensures that no glitches or anything like that passes
through and my state machines don't get triggered. Don't know if it's a
good thing to do but what ever floats the boat, right ? Also, if there's a
better way around lemme know.And also, if anyone knows why this is
happening other than what i think, kindly tell me that also.

thanks    

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

Let's put aside the sync signal and the AND gate, and get back to
basics: is the START signal synchronized to the FSM clock, i.e., has
it been passed through a couple of flip-flops clocked by the FSM clock
before being applied to the FSM?

Is the START signal the same as the reset signal? If not, has the
reset signal been synchronized to the FSM clock?

I'm concerned that you've solved the problem, or perhaps just moved
it, without any real understanding of the underlying failure
mechanism. And that rarely ends well.

Bob Perlman
Cambrian Design Works

 

[salimbaba]

Let's put aside the sync signal and the AND gate, and get back to
basics: is the START signal synchronized to the FSM clock, i.e., has
it been passed through a couple of flip-flops clocked by the FSM clock
before being applied to the FSM?

Is the START signal the same as the reset signal? If not, has the
reset signal been synchronized to the FSM clock?

I'm concerned that you've solved the problem, or perhaps just moved
it, without any real understanding of the underlying failure
mechanism. And that rarely ends well.

Bob Perlman
Cambrian Design Works

Hey Bob,
That's what i am afraid of because for now i have just kind of put it asid
but i know that sometime in future, this thing will come up again, so
need a permanent solution not a way around like the one i have done.An
regarding your questions,

Yes the START signal is synced to FSM clock, 3 flip-flops in the way.

RESET signal is also synced to FSM clock, since i had multiple clock
coming in to the design so i generated a reset synchronizer for eac
clock.
And what to you mean by "
Is the START signal the same as the reset signal?" So kindly help me ou
with it. You people have already done a lot and i really appreciate tha
=)

thanks

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