Guest
On Tuesday, April 21, 2020 at 12:31:58 AM UTC-4, Gerhard Hoffmann wrote:
That sounds like an odd explanation, since I'd think it ought to be
fairly easy to control the wafer's mechanical thickness. And even
if not, surely it doesn't vary anything close to 2:1?
Whatever the explanation, if they could simply separate the parts
into tighter bins it would help us poor slobs a lot.
Earlier this year I grabbed a handful of random J175s (P-ch) from a
bag, for LED current limiters. The Idss spec is all over the map
(7-60mA), but the parts themselves were actually all very close,
about 30 +/-2mA. Okay, that's great. But if it's not guaranteed,
I can't use it.
Cheers,
James Arthur
Am 21.04.20 um 05:37 schrieb jlarkin@highlandsniptechnology.com:
I've seen jfets that were spec's 10:1 for Idss. There is something
strange about the jfet process.
I think that's because the channel has the gate from top
and from bottom/substrate. Thus the mechanical thickness of the wafer
must play a role. That is not so easy to control as diffusion time.
Cheers, Gerhard
That sounds like an odd explanation, since I'd think it ought to be
fairly easy to control the wafer's mechanical thickness. And even
if not, surely it doesn't vary anything close to 2:1?
Whatever the explanation, if they could simply separate the parts
into tighter bins it would help us poor slobs a lot.
Earlier this year I grabbed a handful of random J175s (P-ch) from a
bag, for LED current limiters. The Idss spec is all over the map
(7-60mA), but the parts themselves were actually all very close,
about 30 +/-2mA. Okay, that's great. But if it's not guaranteed,
I can't use it.
Cheers,
James Arthur