The definition of comnatorial prcess?

[glen herrmannsfeldt]

rickman <gnuarm@gmail.com> wrote:

(snip, I wrote)

OK, I suppose I agree with that one. Though I am not so sure that
any of the tools would actually figure it out. Normally, you
use the negedge or posedge (in verilog, or equivalent in VHDL)
that specifically asks for an edge triggered FF.

If you do actually manage with gates and delays to make something
that is logically correct, I would be surprised if it worked at all.

As far as I know, it is usual for the tools to ignore any delay
statements. Without delays, any delay based latch or FF will fail.

I agree 100% that would be hard to create a edge sensitive ff from
logic in an FPGA or elsewhere unless you have a way to assure non-
overlapping clocks. I don't think delay statements (even if they were
not ignored by synthesis), would be enough to fully specify a
correctly working ff. I think a logic description without delay
statements would produce a ff that works in simulation. The problem
is that an implementation would have unknown delays but more
specifically the skew of the clock signals would need to be
controlled. In fact, skew would likely need to be added to make the
two enables (master and slave) each less than 50% duty cycle. It
would be hard to do that with delay statements. But with no delay a
logic simulation would work because of the delta delays I think.

Yes. My understanding from many years ago, and likely from TTL,
is that it is (was) done using two thresholds. As the clock falls
(or rises) two things happen at two different points on the clock
transition. Since the TTL databook has schematics for many
circuits, it might even be possible to see it.

I have no idea if a properly constructed logic description would infer
an edge triggered ff in an FPGA or not. I guess that might just be a
bit too much to expect from the tools.

They are pretty good at figuring out strange logic, but yes,
I think that would be too much.

-- glen