D
Dek
Guest
On 25 Apr, 10:01, "HT-Lab" <han...@ht-lab.com> wrote:
I think I'll try first the idea of KJ; since I'm just learning VHDL
and ModelSim, I'll leave Tcl for the future.
Thanks again
Bye
Dek
Thanks all"Dek" <daniele.deq...@gmail.com> wrote in message
news:c3686086-6f77-4d96-9498-1c21532af85e@3g2000yqk.googlegroups.com...
On 23 Apr, 19:19, Mike Treseler <mtrese...@gmail.com> wrote:
Dek wrote:
I think I can't do anything better, because I have to simulate how an
FPGA would work on data coming from a detector, that are already
stored in many .txt files.
Now the problem is that such files are thousands and it takes a lot of
time to change manually their name in vhdl code. One idea is to use
Generics, name all data files in a "name.do" file and use "do name.do"
command. Even in this case, however, I have to name files manually one
by one. Do you know if there is a way to read all files in a folder
without nameing them?
Look into using Tcl which if fully integrated with Modelsim. To read a
directory simply use the "glob *" command followed by a "foreach" to handle
each filename. Other useful Tcl Modelsim commands are force/when and examine
(see manual),
Hanswww.ht-lab.com
The same problem, unfortunately, is for writing, since for each in-
file I have to write one out-file.
Thanks
Bye- Nascondi testo citato
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I think I'll try first the idea of KJ; since I'm just learning VHDL
and ModelSim, I'll leave Tcl for the future.
Thanks again
Bye
Dek