"tasks" in VerilogA?

[zephyr]

Happy new year everyone!

I searched this group for "veriloga task" and it returned nothing.
Before that I read CDN VA language ref (ver 5.1) several times and
nothing seems promising.

What I am trying to do is to port a test pattern generater from verilog
to veriloga. In the verlog view there are lots of tasks defined so I
can call them any time so I don't need to rewrite the same output
sequences (e.g. a synchronize sequence) every time I use it. However, I
can't find an equivalent in veriloga.

Anybody encountered this before?

Thanks!
-z

 

[Andrew Beckett]

On 2 Jan 2006 14:59:49 -0800, "zephyr" <zephyr750@gmail.com> wrote:

Happy new year everyone!

I searched this group for "veriloga task" and it returned nothing.
Before that I read CDN VA language ref (ver 5.1) several times and
nothing seems promising.

What I am trying to do is to port a test pattern generater from verilog
to veriloga. In the verlog view there are lots of tasks defined so I
can call them any time so I don't need to rewrite the same output
sequences (e.g. a synchronize sequence) every time I use it. However, I
can't find an equivalent in veriloga.

Anybody encountered this before?

Thanks!
-z

There are tasks and functions in Verilog-AMS, but in Verilog-A you just have
analog functions. These are covered in the documentation.

Andrew.

 

[zephyr]

Thanks Andrew. Verilog-AMS would still require a mixed-mode simulation
but I would really like to have a pure spice-level sim. Guess I'm stuck
with loooong bit streams with that approach ...

-z