SystemVerilog Parser crash and conflicts

I'm now working on a parser for SystemVerilog using flex and bison. My parser crashes on all the case blocks (segfaults) and has quite a lot of conflicts regarding generate blocks. I am positive that the problem lies somewhere in the parser file but I am unable to track it down and solve it. Can someone take a look at my parser and help out? The parser is written in C++ and is only supposed to parse a limited portion of SystemVerilog 1800-2009 grammar.

The tar.gz file of the project: https://drive.google.com/file/d/0ByDiaeKPEXm7OFctVWl3dUZSams/edit?usp=sharing

Thanks in advance.