Synthesis of 'X'

[Colin Beighley]

Hello,

Is there a standard way in which the value 'X' assigned to a signal
gets synthesized?

I would assume that it would just trigger a synchronous LUT reset.

Thanks,
Colin

 

[KJ]

On Jul 11, 12:28 pm, Colin Beighley <colinbeigh...@gmail.com> wrote:

Hello,

Is there a standard way in which the value 'X' assigned to a signal
gets synthesized?

Since 'X' is the result of driving '0' and '1' together I would hope
that this would not be synthesizable. I'm guessing though that you
mean 'X' as a "don't care". In that case, I don't think there is a
'standard', but the synthesis tools will report to you what they are
using when they come across your use of 'X'.

However, you mentioned X getting assigned to a signal which implies
you mean
sig <= 'X';
Maybe you meant a don't care which is
sig <= '-';

In either case, you're at the mercy of the synthesis tools which as I
mentioned should report what value it is using for 'X' or '-'.

I would assume that it would just trigger a synchronous LUT reset.

Wow...that is not at all what I would assume.

Kevin Jennings

 

[Tricky]

On Jul 11, 5:28 pm, Colin Beighley <colinbeigh...@gmail.com> wrote:

Hello,

Is there a standard way in which the value 'X' assigned to a signal
gets synthesized?

I would assume that it would just trigger a synchronous LUT reset.

Thanks,
Colin

Given that LUTs are not even resettable, I dont know how you'd come to
this conclusion.

'X's should only ever be used to indicate a problem in simulation,
like this:

if en = '1' then
output <= a;
elsif en = '0' then
output <= 'b;
else
output <= (others => 'X');
end if;

If you really mean dont care, its not until recently that the language
had much support for dont care ('-', not 'X'). now, in VHDL you can
use them in case statements, but thats about it afaik. Before VHDL
2008 it would literally compare the string to dont care, so even if
the bits were '1' or '0', the test would fail.

now you can write:

case? s is
when "00--" =>
--do something with MSBs = 0
when "001-" =>
--etc.

 

[Martin Thompson]

Colin Beighley <colinbeighley@gmail.com> writes:

Hello,

Is there a standard way in which the value 'X' assigned to a signal
gets synthesized?

'X' tends not to be assigned to signals directly - it's the result of
driving a '0' and a '1' at the same time. You *can* assign it yourself,
and synthesis tools *may* treat it as a don't care.

(If you want a don't care, '-' is the VHDL value which you can assign to
a signal/variable. Synthesis tools (IME) will treat it properly and use
that knowledge to optimise logic. Be aware that the normal '=' operator
doesn't work that way though - you have to use std_match)

I would assume that it would just trigger a synchronous LUT reset.

That's an interesting assumption on a few counts:

1) The LUTs are not synchronous

2) *Assuming* you meant a flipflop, the synchronous (or not) nature of a
write to a signal depends on the context in which it's written, not the
value that's written.

3) *Assuming* 'X' were to be representable and assigned in a clocked
process, would the flipflop not just take the value 'X' (as in
simulation) and propagate it to the output?

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware