Switch on LED upon receiving ethernet packets

Currently, I'm trying to execute a program where the LED placed on the FPGA board should switch on after transmitting every 10 Ethernet packets generated from a Linux server. The code I've written is in the following which doesn't work properly. I'm trying to figure out the problem but still undone. Any help would be much appreciated.

---------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all:

---------------------------------------------

entity notification is

port (clk, reset, qdv: in std_logic;
LED: out std_logic
);
end notification;

architecture behavior of notification is
signal qdv_a: std_logic;
signal qdv_b: std_logic;
signal packet_count: std_logic_vector (3 downto 0);


begin

no_1: process(clk, reset)

begin

if (reset = '1') then
qdv_a <= '0';
elsif rising_edge (clk) then
qdv_a <= qdv;
end if;
end process no_1;
qdv_b <= qdv and (not qdv_a);

no_2: process(clk, reset)
begin
if (reset = '1') then
packet_count <= "0000";
elsif rising_edge (clk) then
if qdv_b = '1' then
if packet_count < "1010" then
packet_count <= packet_count + 1;
LED <= '0';
else
LED <= '1';
packet_count <= (others => '0');
end if;
end if;
end if;
end process no_2;

end behavior;

 

[rickman]

You don't say what you are having trouble with. Is the problem in
simulation or in synthesis?

Rick


mamun072009@gmail.com wrote on 11/9/2017 12:56 AM:

Currently, I'm trying to execute a program where the LED placed on the FPGA board should switch on after transmitting every 10 Ethernet packets generated from a Linux server. The code I've written is in the following which doesn't work properly. I'm trying to figure out the problem but still undone. Any help would be much appreciated.

---------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all:

---------------------------------------------

entity notification is

port (clk, reset, qdv: in std_logic;
LED: out std_logic
);
end notification;

architecture behavior of notification is
signal qdv_a: std_logic;
signal qdv_b: std_logic;
signal packet_count: std_logic_vector (3 downto 0);


begin

no_1: process(clk, reset)

begin

if (reset = '1') then
qdv_a <= '0';
elsif rising_edge (clk) then
qdv_a <= qdv;
end if;
end process no_1;
qdv_b <= qdv and (not qdv_a);

no_2: process(clk, reset)
begin
if (reset = '1') then
packet_count <= "0000";
elsif rising_edge (clk) then
if qdv_b = '1' then
if packet_count < "1010" then
packet_count <= packet_count + 1;
LED <= '0';
else
LED <= '1';
packet_count <= (others => '0');
end if;
end if;
end if;
end process no_2;

end behavior;

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

 

[Gabor]

On Thursday, 11/9/2017 12:56 AM, mamun072009@gmail.com wrote:

Currently, I'm trying to execute a program where the LED placed on the FPGA board should switch on after transmitting every 10 Ethernet packets generated from a Linux server. The code I've written is in the following which doesn't work properly. I'm trying to figure out the problem but still undone. Any help would be much appreciated.

---------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all:

---------------------------------------------

entity notification is

port (clk, reset, qdv: in std_logic;
LED: out std_logic
);
end notification;

architecture behavior of notification is
signal qdv_a: std_logic;
signal qdv_b: std_logic;
signal packet_count: std_logic_vector (3 downto 0);


begin

no_1: process(clk, reset)

begin

if (reset = '1') then
qdv_a <= '0';
elsif rising_edge (clk) then
qdv_a <= qdv;
end if;
end process no_1;
qdv_b <= qdv and (not qdv_a);

no_2: process(clk, reset)
begin
if (reset = '1') then
packet_count <= "0000";
elsif rising_edge (clk) then
if qdv_b = '1' then
if packet_count < "1010" then
packet_count <= packet_count + 1;
LED <= '0';
else
LED <= '1';
packet_count <= (others => '0');
end if;
end if;
end if;
end process no_2;

end behavior;

Just a guess, since you didn't say how it fails, but if qdv is not
synchronous to clk, then you will potentially miss some packets
in the count. The result would be an LED that comes on after
every Nth packet, where N is greater or equal to 10.



--
Gabor

 

[Charles Bailey]

On 2017-11-08 23:56, mamun072009@gmail.com wrote:

Currently, I'm trying to execute a program where the LED placed on the FPGA board should switch on after transmitting every 10 Ethernet packets generated from a Linux server. The code I've written is in the following which doesn't work properly. I'm trying to figure out the problem but still undone. Any help would be much appreciated.

---------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all:

---------------------------------------------

entity notification is

port (clk, reset, qdv: in std_logic;
LED: out std_logic
);
end notification;

architecture behavior of notification is
signal qdv_a: std_logic;
signal qdv_b: std_logic;
signal packet_count: std_logic_vector (3 downto 0);


begin

no_1: process(clk, reset)

begin

if (reset = '1') then
qdv_a <= '0';
elsif rising_edge (clk) then
qdv_a <= qdv;
end if;
end process no_1;
qdv_b <= qdv and (not qdv_a);

no_2: process(clk, reset)
begin
if (reset = '1') then
packet_count <= "0000";
elsif rising_edge (clk) then
if qdv_b = '1' then
if packet_count < "1010" then
packet_count <= packet_count + 1;
LED <= '0';
else
LED <= '1';
packet_count <= (others => '0');
end if;
end if;
end if;
end process no_2;

end behavior;

"packet_count <= packet_count + 1;"
I'm surprised that this compiles successfully. The "+" operator is not
defined for std_logic_vector. However the "+" operator IS defined for
unsigned type, which is part of the number_std package. Try declaring
packet_count like this:
signal packet_count: unsigned(3 downto 0);

I would also suggest combining the two processes into a single process.

Charles Bailey

 

[Charles Bailey]

On 2017-11-08 23:56, mamun072009@gmail.com wrote:

Currently, I'm trying to execute a program where the LED placed on the FPGA board should switch on after transmitting every 10 Ethernet packets generated from a Linux server. The code I've written is in the following which doesn't work properly. I'm trying to figure out the problem but still undone. Any help would be much appreciated.

Or, here is how I would recode the whole thing:

---------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all:

---------------------------------------------

entity notification is

port (clk, reset, qdv: in std_logic;
LED: out std_logic
);
end notification;

architecture behavior of notification is
signal qdv_a, qdv_b, qdv_p : std_logic;
signal packet_count: integer range 0 to 9;

begin

no_1: process(clk)
begin
if rising_edge (clk) then
qdv_a <= qdv;
if (reset = '1') then
qdv_b <= qdv;
LED <= '0';
packet_count <= 0;
else
qdv_b <= qdv_a;
if qdv_p = '1' then
if packet_count = 9 then
LED <= '1';
packet_count <= 0;
else
packet_count <= packet_count + 1;
LED <= '0';
end if;
end if;
end if;
end if;
end process no_1;
qdv_p <= qdv_a and (not qdv_b);

end behavior;


Charles Bailey

 

[rickman]

Charles Bailey wrote on 11/30/2017 5:26 PM:

On 2017-11-08 23:56, mamun072009@gmail.com wrote:
Currently, I'm trying to execute a program where the LED placed on the
FPGA board should switch on after transmitting every 10 Ethernet packets
generated from a Linux server. The code I've written is in the following
which doesn't work properly. I'm trying to figure out the problem but
still undone. Any help would be much appreciated.

Or, here is how I would recode the whole thing:

Or, better yet.


> ---------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all:

---------------------------------------------

entity notification is

port (clk, reset, qdv: in std_logic;
LED: out std_logic
);
end notification;

architecture behavior of notification is
signal qdv_a, qdv_b, qdv_p : std_logic;
signal packet_count: integer range 0 to 9;

begin

no_1: process(clk)
begin
if rising_edge (clk) then
qdv_a <= qdv;
if (reset = '1') then
qdv_b <= qdv;
LED <= '0';
packet_count <= 0;
else
qdv_b <= qdv_a;
if qdv_p = '1' then
if packet_count-1 < 0 then
LED <= '1';
packet_count <= 9;
else
packet_count <= packet_count - 1;
LED <= '0';
end if;
end if;
end if;
end if;
end process no_1;
qdv_p <= qdv_a and (not qdv_b);

end behavior;

Most FPGA devices (assuming this will be in an FPGA) have dedicated carry
chains. The above logic gives the tools the chance to utilize the carry
chain for the comparison (free logic) and may run faster too.

If the tools have trouble understanding that the two uses of packet_count-1
can use the same logic, you may need to create a new signal and assign
packet_count-1 to it explicitly then use that signal in the comparison and
the assignment.

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998