Guest
On Apr 25, 9:31 am, "Joel Koltner" <zapwireDASHgro...@yahoo.com>
wrote:
http://www.tarayinc.com/
You do minimal floorplanning right in the tool, and it optimizes the I/
O assignment for the specific electrical characteristics of the
device, and the arrangements of the other major devices the FPGA is
connected to. Works with both Cadence and Mentor schematics. The nice
part is that the EE doesn't have to actually do any PCB layout, but it
makes the layout flow much better (fewer vias, layers, shorter
connections, etc).
-Brian
wrote:
There's a new tool on the market for this - Taray's 7 Circuits"JosephKK" <quiettechb...@yahoo.com> wrote in message
news20314pl6k3565m260fkarco8n63bpb5hb@4ax.com...
That does sound specific to one particular tool (vendors's software).
Yeah, after Dave posted that I checked and unfortunately Pulsonix can't do
it... although it's "close enough" that I imagine adding it as a feature
wouldn't be particularly difficult. I think it's a good idea -- hopefully it
will show up in more tools over time.
http://www.tarayinc.com/
You do minimal floorplanning right in the tool, and it optimizes the I/
O assignment for the specific electrical characteristics of the
device, and the arrangements of the other major devices the FPGA is
connected to. Works with both Cadence and Mentor schematics. The nice
part is that the EE doesn't have to actually do any PCB layout, but it
makes the layout flow much better (fewer vias, layers, shorter
connections, etc).
-Brian