Stumped in Simulation Land

S

Shannon

Guest
OK, this could NOT be more simple. Here is my code. A simple
counter:

rep_rate : process(system_clock, Reset)
begin
if (Reset = '1') then
RepRate_Count <= to_unsigned(0,RepRate_Count'LENGTH);
elsif rising_edge(system_clock) then
Itrig <= '0';
if (RepRate_Count < to_unsigned
(SYSTEM_FREQUENCY,RepRate_Count'LENGTH)) then
RepRate_Count <= RepRate_Count + RepRate;
else
RepRate_Count <= RepRate;
Itrig <= '1';
end if;
end if;
end process;

trig_out <= Itrig;

This should produce single clock-wide pulses separated by 1/RepRate.
ModelSim however shows in gate simulation that the Itrig pulses are
LESS than one SYSTEM_FREQUENCY period long. How is this
possible????? SYSTEM_FREQUENCY is 250MHz (T= 4ns) and trig_out high
time is 3.773ns. I don't get it. The pulse separation is spot on.

Shannon
 
Shannon wrote:
OK, this could NOT be more simple. Here is my code. A simple
counter:

rep_rate : process(system_clock, Reset)
begin
if (Reset = '1') then
RepRate_Count <= to_unsigned(0,RepRate_Count'LENGTH);
elsif rising_edge(system_clock) then
Itrig <= '0';
if (RepRate_Count < to_unsigned
(SYSTEM_FREQUENCY,RepRate_Count'LENGTH)) then
RepRate_Count <= RepRate_Count + RepRate;
else
RepRate_Count <= RepRate;
Itrig <= '1';
end if;
Click to expand...
trig_out <= Itrig;

end if;
end process;

-- trig_out <= Itrig;
Click to expand...
 
On Jul 29, 11:07 am, Shannon <sgo...@sbcglobal.net> wrote:
OK, this could NOT be more simple.  Here is my code.  A simple
counter:

rep_rate : process(system_clock, Reset)
begin
        if (Reset = '1') then
                        RepRate_Count <= to_unsigned(0,RepRate_Count'LENGTH);
        elsif rising_edge(system_clock) then
                Itrig <= '0';
                if (RepRate_Count < to_unsigned
(SYSTEM_FREQUENCY,RepRate_Count'LENGTH)) then
                        RepRate_Count <= RepRate_Count + RepRate;
                else
                        RepRate_Count <= RepRate;
                        Itrig <= '1';
                end if;
        end if;
end process;

trig_out <= Itrig;

This should produce single clock-wide pulses separated by 1/RepRate.
ModelSim however shows in gate simulation that the Itrig pulses are
LESS than one SYSTEM_FREQUENCY period long.  How is this
possible?????  SYSTEM_FREQUENCY is 250MHz (T= 4ns) and trig_out high
time is 3.773ns.  I don't get it.  The pulse separation is spot on.

Shannon
Click to expand...
Gate simulation could be showing faster falling delay than rising
delay on the signal driver. Especially since your separation is spot
on. Check your clock to signal rise/fall times and you'll see what I'm
talking about.

Andy
 
On Jul 29, 10:16 am, Andy <jonesa...@comcast.net> wrote:
On Jul 29, 11:07 am, Shannon <sgo...@sbcglobal.net> wrote:



OK, this could NOT be more simple.  Here is my code.  A simple
counter:

rep_rate : process(system_clock, Reset)
begin
        if (Reset = '1') then
                        RepRate_Count <= to_unsigned(0,RepRate_Count'LENGTH);
        elsif rising_edge(system_clock) then
                Itrig <= '0';
                if (RepRate_Count < to_unsigned
(SYSTEM_FREQUENCY,RepRate_Count'LENGTH)) then
                        RepRate_Count <= RepRate_Count + RepRate;
                else
                        RepRate_Count <= RepRate;
                        Itrig <= '1';
                end if;
        end if;
end process;

trig_out <= Itrig;

This should produce single clock-wide pulses separated by 1/RepRate.
ModelSim however shows in gate simulation that the Itrig pulses are
LESS than one SYSTEM_FREQUENCY period long.  How is this
possible?????  SYSTEM_FREQUENCY is 250MHz (T= 4ns) and trig_out high
time is 3.773ns.  I don't get it.  The pulse separation is spot on.

Shannon

Gate simulation could be showing faster falling delay than rising
delay on the signal driver. Especially since your separation is spot
on. Check your clock to signal rise/fall times and you'll see what I'm
talking about.

Andy
Click to expand...
Bingo Andy! You nailed it. The difference between the rising delay
and falling delay is exactly 227ps. Very interesting. So since I
learned something new today can I take the rest of the day off?

Shannon
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top