std_logic_vector clock delay format

[Brad Smallridge]

What is the best way to write a
series of delayed std_logic_vectors
to replace the verbose code below:

if(clk'event and clk='1')then
data_1 <= data_in;
data_2 <= data_1;
data_3 <= data_2;
etc.

Thanks,
Brad Smallridge
aivision

 

[Mike Treseler]

Brad Smallridge wrote:

What is the best way to write a
series of delayed std_logic_vectors
to replace the verbose code below:

if(clk'event and clk='1')then
data_1 <= data_in;
data_2 <= data_1;
data_3 <= data_2;
etc.

It may not be best, or less verbose,
but I would declare a register array like this:

subtype reg_t is std_logic_vector(reg_len_c-1 downto 0);
type regs_t is array (0 to array_len_c-1) of reg_t;
variable regs_v : regs_t;

And update it something like this:

regs_v := d & regs_v(0 to array_len_c-2); -- push D into r0

see register stack source here for a related example:
http://mysite.verizon.net/miketreseler/

Good luck.

-- Mike Treseler

 

[Jonathan Bromley]

On Sun, 4 Jan 2009 19:49:22 -0800, "Brad Smallridge" wrote:

What is the best way to write a
series of delayed std_logic_vectors
to replace the verbose code below:

if(clk'event and clk='1')then
data_1 <= data_in;
data_2 <= data_1;
data_3 <= data_2;
etc.

hi Brad

As Mike said, you could make an array for your
numerous delay stages. Alternatively, if this is
a requirement you meet often, you could consider
packaging the whole mess as a block or even as an
entity. It could be a procedure too, but the form
of procedure you would need is unlikely to be
synthesisable.

Here's the entity flavour:

entity delay_line is
generic (stages: positive := 1);
port (clock: in std_logic;
d_in: in std_logic_vector; -- unconstrained
d_out: out std_logic_vector -- unconstrained
);
end;
architecture RTL of delay_line is
subtype data_vec is std_logic_vector(d_in'range);
type delay_line_array is array (1 to stages) of data_vec;
signal the_delay_line: delay_line_array;
begin
-- protect yourself against stupidity
assert d_in'length = d_out'length
report "Input and output vectors must be same size"
severity FAILURE;
-- usual clocked process
process(clock)
begin
if rising_edge(clock) then
the_delay_line <= d_in & the_delay_line(1 to stages-1);
end if;
end process;
-- expose the last stage as output
d_out <= the_delay_line(stages);
end;

Now the verbosity is hidden and you can just instantiate it
anywhere you need it:

my_delayer: entity work.delay_line
generic map (stages => 3)
port map (clock => clk, d_in => data_in, d_out => result);

And the delay_line entity resizes itself to suit whatever
size of std_logic_Vector you connect to its ports, so long
as the input and output are the same width.

I don't know whether this helps with your real needs,
and you need to check my code for typos because I
haven't tested it. Also, you will get (harmless) warning
messages about a null range for the array slice
the_delay_line(1 to stages-1)
in the special case where stages=1, but I'm guessing you
probably wouldn't bother with such a thing in any case
when you want only one delay stage.

cheers
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

Jonathan Bromley wrote:

As Mike said, you could make an array for your
numerous delay stages. Alternatively, if this is
a requirement you meet often, you could consider
packaging the whole mess as a block or even as an
entity. It could be a procedure too, but the form
of procedure you would need is unlikely to be
synthesisable.

I would agree that a packaged procedure
is not worth the overhead in this case.
If the array dimensions are
constrained by a package or generic,
then the update procedure is a one-liner.

Here's the entity flavour:

Nice example using unconstrained ports.

I don't know whether this helps with your real needs,
and you need to check my code for typos because I
haven't tested it.

Your code worked for me.

-- Mike Treseler

 

Hi,

Please note that unconstrained ports are not (currently) supported by
Xilinx tools (ISE/Xst 10.1.03).

Best regards.

 

[Jonathan Bromley]

On Tue, 6 Jan 2009 02:41:26 -0800 (PST), no_spa2005@yahoo.fr wrote:

Please note that unconstrained ports are not (currently) supported by
Xilinx tools (ISE/Xst 10.1.03).

I don't have ISE10 installed but I tried it in 8.2 and you're
at least partly right: it's OK to have unconstrained ports,
but the 'range attribute of an unconstrained port is not
correctly supported. This sucks and Xilinx need to fix
it ASAP. However, it's easy to work around because
the 'length attribute of an unconstrained port IS
correctly supported, so if you change just this one line
in the code I posted:

--subtype data_vec is std_logic_vector(d_in'range);
subtype data_vec is std_logic_vector(d_in'length-1 downto 0);

then everything works correctly.

Obviously you cannot have unconstrained ports on your
top-level entity. That's not a Xilinx limitation, it's
simply common sense. But unconstrained ports on inner
entities are fine and good; I can't imagine designing
without them.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

Hi Jonathan,

Thanks ! you're right, it works with length attribute. With range
attribute, you have :
FATAL_ERROR:Xstortability/export/Port_Main.h:143:1.17 - This
application has discovered an exceptional condition from which it
cannot recover. Process will terminate. For technical support on this
issue, please open a WebCase with this project attached at
http://www.xilinx.com/support.

Very helpful message !
In Xilinx documentation (xst.pdf, p494), about XST VHDL Language
Support, it's written : Ports : Supported (no unconstrained ports).
May be you can check in 8.2 documentation if it's the same. So it's
not "officially" supported. May be if we are several to open a Webcase
they will perhaps correct this bug ? (...)
Regards.