J
JB
Guest
Hello all,
I struggle with an issue I can't understand the root cause.
When simulating my back annoted design with modelsim, I get unexpected
behavior when using a simulation step of 1ns, but no errors when using
a step of 1ps.
My design is running at 1MHz (so I expect a simulation step of 1ns to
be highly sufficient).
The part that is causing trouble is a wrapper around an SRAM instance
(it is an actel RAM512x18 component on an actel proasic3 FPGA).
I've got the exact same component instanciated in the exact same
wrapper simulating fine on an actel igloo FPGA. I am aware that place
and route may have produce significantly different results between the
two FPGAs and that having the design running smoothly on one FPGA
don't prove anything.
Still I can't figure out why modelsim would not simulate identically
using a 1ns or 1ps step.
Last but not least, I've got no warning from modelsim (no glitch
found).
If any of you have an idea of what could be happening there I would be
glad to ear it.
Regards
I struggle with an issue I can't understand the root cause.
When simulating my back annoted design with modelsim, I get unexpected
behavior when using a simulation step of 1ns, but no errors when using
a step of 1ps.
My design is running at 1MHz (so I expect a simulation step of 1ns to
be highly sufficient).
The part that is causing trouble is a wrapper around an SRAM instance
(it is an actel RAM512x18 component on an actel proasic3 FPGA).
I've got the exact same component instanciated in the exact same
wrapper simulating fine on an actel igloo FPGA. I am aware that place
and route may have produce significantly different results between the
two FPGAs and that having the design running smoothly on one FPGA
don't prove anything.
Still I can't figure out why modelsim would not simulate identically
using a 1ns or 1ps step.
Last but not least, I've got no warning from modelsim (no glitch
found).
If any of you have an idea of what could be happening there I would be
glad to ear it.
Regards