Spice COMS Invertor?

N. Thornton · Nov 17, 2004

Hi

I'm looking for a spice model for a CMOS invertor for analogue use. It
needs to reproduce the non linear gain, and the gates' significant
output impedance. It also needs to be run on other than just 5v.

The invertor that comes with LTspice is nothing like this, and is
entirely unsuitable.

I've googled, but found nothing yet. Anyone, anywhere?

NT

PS I've used Spice very little so expect idiot responses

Jim Thompson · Nov 17, 2004

On 17 Nov 2004 13:37:10 -0800, bigcat@meeow.co.uk (N. Thornton) wrote:

Hi

I'm looking for a spice model for a CMOS invertor for analogue use. It
needs to reproduce the non linear gain, and the gates' significant
output impedance. It also needs to be run on other than just 5v.

The invertor that comes with LTspice is nothing like this, and is
entirely unsuitable.

I've googled, but found nothing yet. Anyone, anywhere?

NT

PS I've used Spice very little so expect idiot responses

I have the original 'HCU04 stuff (since I redesigned it for ON-Semi).

It may, or may not, work on your simulator, since it relies on a lot
of parameter passing.

What I'd recommend is making your own inverter by pulling generic CMOS
devices from your simulator's library, set width wider until threshold
is mid-supply, and then experiment from there.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice

480)460-2350 | |
| E-mail Address at Website Fax

Joerg · Nov 17, 2004

Hi N. Thornton,

If you are eyeing the unbuffered HC04 version you might be able to
obtain it from a manufacturer. Fairchild offers these. They are not
PSpice but HSpice files so you'd have to parse through by hand. I am not
familiar with HSpice so it may or may not be a big deal to do. Also, I
believe they send them to you "as is" and require you not to divulge it
to other parties and agree to some other conditions. Check it out:

http://www.fairchildsemi.com/models/HSPICE/Interface_and_Logic/HC.html

Regards, Joerg

http://www.analogconsultants.com

Jim Thompson · Nov 17, 2004

On Wed, 17 Nov 2004 22:58:40 GMT, Joerg
<notthisjoergsch@removethispacbell.net> wrote:

Hi N. Thornton,

If you are eyeing the unbuffered HC04 version you might be able to
obtain it from a manufacturer. Fairchild offers these. They are not
PSpice but HSpice files so you'd have to parse through by hand. I am not
familiar with HSpice so it may or may not be a big deal to do. Also, I
believe they send them to you "as is" and require you not to divulge it
to other parties and agree to some other conditions. Check it out:

http://www.fairchildsemi.com/models/HSPICE/Interface_and_Logic/HC.html

Regards, Joerg

http://www.analogconsultants.com

That's the shits... the model has "protected" (encrypted) device
models, meaning it will only run on HSpice :-(

I guess I'll have to get out my 'HCU04 design and patch all the
oddball "Shrink" and other parameter passing, make it
Spice-flavor-independent and post it.

_Maybe_ this weekend.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice

480)460-2350 | |
| E-mail Address at Website Fax

Joerg · Nov 18, 2004

Hi Jim,

That's the shits... the model has "protected" (encrypted) device
models, meaning it will only run on HSpice :-(

Maybe the Philips versions (Berkeley Spice) would work and save your
weekend. However, I haven't looked at these myself yet. There are 74HC
but no CD4000 models:

http://www.standardproducts.philips.com/support/spice/#

I guess I'll have to get out my 'HCU04 design and patch all the
oddball "Shrink" and other parameter passing, make it
Spice-flavor-independent and post it.

_Maybe_ this weekend.

But then everyone who uses it and comes through Phoenix later should
treat you for a Widmer's on tap at the local pub

Regards, Joerg

http://www.analogconsultants.com

Active8 · Nov 18, 2004

On Wed, 17 Nov 2004 16:28:32 -0700, Jim Thompson wrote:
<snip>

That's the shits... the model has "protected" (encrypted) device
models, meaning it will only run on HSpice :-(

I guess I'll have to get out my 'HCU04 design and patch all the
oddball "Shrink" and other parameter passing, make it
Spice-flavor-independent and post it.

You know what would really be the balls? A short example of how you

hack your .cir files, pass params, and all that stuff you do to run
worst case. Maybe that first design challenge you issued, if you get
a chance.

--
Best Regards,
Mike

Kevin Aylward · Nov 18, 2004

Jim Thompson wrote:

On 17 Nov 2004 13:37:10 -0800, bigcat@meeow.co.uk (N. Thornton) wrote:

Hi

I'm looking for a spice model for a CMOS invertor for analogue use.
It needs to reproduce the non linear gain, and the gates' significant
output impedance. It also needs to be run on other than just 5v.

The invertor that comes with LTspice is nothing like this, and is
entirely unsuitable.

I've googled, but found nothing yet. Anyone, anywhere?

Not sure where this post came from, or if I have already replied or not.
Anyway, as usuall, I have a full complement of analogue versions CMOS
inverters, gates, switches and stuff in my SuperSpice download.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

N. Thornton · Nov 18, 2004

Jim Thompson <thegreatone@example.com> wrote in message news:<r1vnp09srqfgjm78p4k300qk4ftrta55ei@4ax.com>...

On Thu, 18 Nov 2004 01:08:14 GMT, Joerg
notthisjoergsch@removethispacbell.net> wrote:

Maybe the Philips versions (Berkeley Spice) would work and save your
weekend. However, I haven't looked at these myself yet. There are 74HC
but no CD4000 models:

http://www.standardproducts.philips.com/support/spice/#

Those look AOK, except they're LEVEL=3, so a bit lacking for high
speed simulations.

I guess I'll have to get out my 'HCU04 design and patch all the
oddball "Shrink" and other parameter passing, make it
Spice-flavor-independent and post it.

_Maybe_ this weekend.

But then everyone who uses it and comes through Phoenix later should
treat you for a Widmer's on tap at the local pub

Regards, Joerg

http://www.analogconsultants.com

Such a deal ;-)

...Jim Thompson

Hi again. What I'm actually looking for is 4000 series invertors. I
understood at least some of what you folks said - I really am a spice
cadet when it comes to spice. I used to do paper design and lash up
rather than simulate, and now I want to learn spice and sim a few
ideas, since I intend to get back into tronics again next year. I'm
sure once I've got the hang of it it'll be quicker and more
informative than lashups, not to mention easier. I've got LTspice at
the mo.

Why 4000? Vdd upto 15v, cheap and easily available, and more than fast
enough. 74HC and HCT doesnt do the voltage.

I know LTSPice comes with invertors, but the documentation describes
them as not even a bit suitable, having no modeling of linear gain,
only switching, 0 or 1v out, no output impedance, no ability to alter
supply V, and no nonlinearity. So all in all no use for analogue as
far as I can tell. As far as rewriting its behaviour, I wouldnt have a
clue.

Thanks for trying to clue me up

NT

Paul Burridge · Nov 18, 2004

On 18 Nov 2004 03:46:23 -0800, bigcat@meeow.co.uk (N. Thornton) wrote:

I know LTSPice comes with invertors, but the documentation describes
them as not even a bit suitable, having no modeling of linear gain,
only switching, 0 or 1v out, no output impedance, no ability to alter
supply V, and no nonlinearity. So all in all no use for analogue as
far as I can tell. As far as rewriting its behaviour, I wouldnt have a
clue.

I would have thought it would have been a relatively simple matter to
create your own model for something as basic as a gate (even with
fullish operational characteristics). But since you're a Spice virgin,
you'd need someone with a bit of experience to guide you. Helmut
springs to mind...
(I'll cross post to sec and you may like to check out the LTSpice
users' group on Yahoo).
--

"What is now proved was once only imagin'd." - William Blake, 1793.

Joerg · Nov 18, 2004

Hi Jim,

Thus, to do process corner simulations, I just concatenate a bunch of
.CIR files, each with the library/temperature/voltage combination I
want... sometimes as many as 30-40 combinations. PSpice will show all
the outputs on a single screen.... making for nice presentations to
the customer.

30-40 on one slide, that's a lot. Just make sure that nobody in the
audience is color blind. Seriously, I had that happen a couple of times.
And the "morse code pattern" only goes so far for folks sitting in the
back rows.

Regards, Joerg

http://www.analogconsultants.com

Keith Williams · Nov 18, 2004

In article <ikspp09613qo26l8ej2rvsolouhccnlmm1@4ax.com>,
thegreatone@example.com says...

On Thu, 18 Nov 2004 13:54:40 -0500, Keith Williams <krw@att.bizzzz
wrote:

In article <8qkpp0hjhr7qklj41ttnjoqhc6m543sn4i@4ax.com>,
thegreatone@example.com says...
On Thu, 18 Nov 2004 11:11:38 -0500, Keith Williams <krw@att.bizzzz
wrote:

In article <uffpp0p7i7gqq1v8u7jj0ki9ffbfdba78r@4ax.com>,
thegreatone@example.com says...
[snip]

As for worst case, I don't do Monte Carlo, because, in an IC,
components of a given type don't wander relative to each other.

Sure they do, with the added complication of device tracking.

Device tracking problems are only an issue with amateur designers ;-)

Tracking problems don't exist? You must live in a charmed world of
perfection. However, I must say that I no longer do circuit design,
so... ;-)

Devices that are located a few microns apart DO tend to track...
designers who rely on tracking cross-chip are fools ;-)

Devices across chip *tend* to track too, just not as well as those next
door. It's all a matter of degree. Nothing is perfect. I always
modeled tracking even with "identical" devices right next door. I
suppose it depends on how good the models are, whether the difference
is apparent.

Monte
Carlo is used quite heavily in IC design.

Almost always I am provided (by the foundry) with device libraries
that cover the worst case process corners.

Sure, but end-point analysis just cuts down on CPU cycles. ;-) I've
used both at the same time (end-point distributions chugged into Monte
Carlo analysis).

Thus, to do process corner simulations, I just concatenate a bunch of
.CIR files, each with the library/temperature/voltage combination I
want... sometimes as many as 30-40 combinations. PSpice will show all
the outputs on a single screen.... making for nice presentations to
the customer.

That's not much different than the above (Monte Carlo using worst-case
numbers).

In all my years in IC design I have seen ONLY ONE foundry that
provided models with Monte-Carlo-specified parameters, and that was
from a village-idiot foundry that took their GUESSED-AT models and
added deviations ;-)

All the models I've seen have parameters useful for such simulation and
I suppose I've called our foundry folks worse things. ;-0

Sure. I get pages and pages of parameters, but they're not
Monte-Carlo-based, they're parameter passing for the specific library
corner. For example:

***************** CORNER_LIB OF TNTP MODEL ***************
*.LIB TT_33
.param
+toxn_33 = 7.15E-09 toxp_33 = 7.15E-09
+dvthn_33 = 0 dvthp_33 = 0
+dwvthn_33 = 0 dwvthp_33 = 0
+dxl_33 = 0 dxw_33 = 0
+cjn_33 = 0.00091 cjp_33 = 0.001267
+cjswn_33 = 1.180E-10 cjswp_33 = 0.740E-10
+cjswgn_33 = 2.310E-10 cjswgp_33 = 1.590E-10
+cgon_33 = 2.920E-10 cgop_33 = 2.440E-10
+hdifn_33 = 1.30E-07 hdifp_33 = 1.30E-07
*.ENDL TT_33
**********************************************************
.LIB C:\PSpice\DeviceLib\SomeFAB\CurrentModels\CMOSdoodah.lib
**********************************************************
.PARAM XLN = {0+dxl_33} XWN = {1E-8+dxw_33}
+ XLP = {5E-9+dxl_33} XWP = {1E-8+dxw_33}
**********************************************************

The models I've used have the distribution specified (mean and sigma,
at least, if not a distribution function). Indeed one can specify
where within the process one wants to run. Want to center at +3sigma?
Go fer it, here's the bill. ;-)

Again, it's been a while since I've actually done circuit design (and
that was bipolar), but I haven't noticed the world change too much.
Perhaps I'll wander off and bug a circuit designer if I get a few
minutes before everyone (me included

leaves for the holiday.

--
Keith

Jim Thompson · Nov 18, 2004

On Thu, 18 Nov 2004 14:44:05 -0500, Keith Williams <krw@att.bizzzz>
wrote:

[snip]

The models I've used have the distribution specified (mean and sigma,
at least, if not a distribution function). Indeed one can specify
where within the process one wants to run. Want to center at +3sigma?
Go fer it, here's the bill. ;-)

Again, it's been a while since I've actually done circuit design (and
that was bipolar), but I haven't noticed the world change too much.
Perhaps I'll wander off and bug a circuit designer if I get a few
minutes before everyone (me included leaves for the holiday.

Keith, Maybe I'm confusing you with another lurker, but aren't you
with IBM Burlington?

I just checked my 4S+ and 6HP libraries... they're parameterized just
like my illustration... no MC variables.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice

480)460-2350 | |
| E-mail Address at Website Fax

Jim Thompson · Nov 18, 2004

On Thu, 18 Nov 2004 15:31:02 -0500, Keith Williams <krw@att.bizzzz>
wrote:

In article <sjvpp0plb2q2jde0qk5t16gbtegqfkk9ir@4ax.com>,
thegreatone@example.com says...
[snip]

Keith, Maybe I'm confusing you with another lurker, but aren't you
with IBM Burlington?

Sure, but have never dealt with ASICs (or foundry for that matter).

I just checked my 4S+ and 6HP libraries... they're parameterized just
like my illustration... no MC variables.

I've never seen ASIC models (and those are *antiques* ;-), only those
for the internal processes (which are somewhat different). Now you
have my interest. I'll have to take a look at the models we use these
days. The ones I used had distribution functions for the various
parameters, including tracking. Perhaps that's gotten too expensive?
Perhaps I've been out of that end of the biz too long (quite likely).

My! Time sure flies when you're having fun... 4S+ is dated 1995 and
6HP is dated 2001.

I was in Burlington one time just a week before Christmas. The hotel
I was in featured food by the New England Culinary Institute (if I
recall the name correctly)... yummy!

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice

480)460-2350 | |
| E-mail Address at Website Fax

Jim Thompson · Nov 18, 2004

On Thu, 18 Nov 2004 16:07:41 -0500, Keith Williams <krw@att.bizzzz>
wrote:

In article <832qp0t4h8f4o0132pat2emvgi7971a95r@4ax.com>,
thegreatone@example.com says...
[snip]
I was in Burlington one time just a week before Christmas. The hotel
I was in featured food by the New England Culinary Institute (if I
recall the name correctly)... yummy!

Yes, Inn at Essex and NECI (which is at the Inn). I live in Essex
about a mile on the other side of the hotel (relative to the IBM site).
Other than taxes and being a true-blue state (first to flip), it's a
nice place to live, four months of the year.

480)460-2350 | |
| E-mail Address at Website Fax

N. Thornton · Nov 19, 2004

"Emoneg" <and@nothere.net> wrote in message news:<ix2nd.53$6q3.41@newsfe6-win.ntli.net>...

*********
.SUBCKT 4069UB 6 1 4
*Connections e s Vcc
M2 1 6 0 0 CD4069BN
M3 1 6 4 4 CD4069BP
.MODEL CD4069BN NMOS (LEVEL=1 VTO=2.1 KP=2.9M GAMMA=3.97U
+ PHI=.75 LAMBDA=1.87M RD=20.2 RS=184.1 IS=31.2F PB=.8 MJ=.46
+ CBD=47.6P CBS=57.2P CGSO=70.2N CGDO=58.5N CGBO=96.3N)
.MODEL CD4069BP PMOS (LEVEL=1 VTO=-2.9 KP=2M GAMMA=3.97U
+ PHI=.75 LAMBDA=1.87M RD=28.2 RS=145.2 IS=31.2F PB=.8 MJ=.46
+ CBD=47.6P CBS=57.2P CGSO=70.2N CGDO=58.5N CGBO=96.3N)
.ENDS 4069UB
*$
*
*************

In LTSPICE

Version 4
SHEET 1 1240 680
WIRE 144 160 96 160
WIRE 96 160 96 288
WIRE 96 432 144 432
WIRE 192 352 192 288
WIRE 192 144 192 112
WIRE 192 448 192 480
WIRE 96 288 48 288
WIRE 96 288 96 432
WIRE 192 288 240 288
WIRE 192 288 192 240
FLAG 192 112 VDD
IOPIN 192 112 In
FLAG 192 480 VDD
IOPIN 192 480 In
FLAG 48 288 IN
IOPIN 48 288 In
FLAG 240 288 OUT
IOPIN 240 288 Out
SYMBOL nmos 144 352 R0
WINDOW 0 57 39 Left 0
WINDOW 3 58 60 Left 0
SYMATTR InstName M2
SYMATTR Value CD4069BN
SYMBOL pmos 144 240 M180
WINDOW 0 60 59 Left 0
WINDOW 3 59 34 Left 0
SYMATTR InstName M1
SYMATTR Value CD4069BP
TEXT 336 232 Left 0 !.MODEL CD4069BN NMOS (LEVEL=1 VTO=2.1 KP=2.9M
GAMMA=3.97U\n+ PHI=.75 LAMBDA=1.87M RD=20.2 RS=184.1 IS=31.2F PB=.8
MJ=.46\n+ CBD=47.6P CBS=57.2P CGSO=70.2N CGDO=58.5N CGBO=96.3N)\n.MODEL
CD4069BP PMOS (LEVEL=1 VTO=-2.9 KP=2M GAMMA=3.97U\n+ PHI=.75 LAMBDA=1.87M
RD=28.2 RS=145.2 IS=31.2F PB=.8 MJ=.46\n+ CBD=47.6P CBS=57.2P CGSO=70.2N
CGDO=58.5N CGBO=96.3N)

OK, it's a bit of a hack but someone else might tidy it up.

DNA

Aha! Looks promising... now what do I do with that bit of text to make
a component model with it? I'm putting the circuit in using circuit
piccies, not using a netlist.

Thanks, NT

Emoneg · Nov 19, 2004

"N. Thornton" <bigcat@meeow.co.uk> wrote in message
news:a7076635.0411181739.535b62a4@posting.google.com...

"Emoneg" <and@nothere.net> wrote in message
news:<ix2nd.53$6q3.41@newsfe6-win.ntli.net>...

*********
.SUBCKT 4069UB 6 1 4
*Connections e s Vcc
M2 1 6 0 0 CD4069BN
M3 1 6 4 4 CD4069BP
.MODEL CD4069BN NMOS (LEVEL=1 VTO=2.1 KP=2.9M GAMMA=3.97U
+ PHI=.75 LAMBDA=1.87M RD=20.2 RS=184.1 IS=31.2F PB=.8 MJ=.46
+ CBD=47.6P CBS=57.2P CGSO=70.2N CGDO=58.5N CGBO=96.3N)
.MODEL CD4069BP PMOS (LEVEL=1 VTO=-2.9 KP=2M GAMMA=3.97U
+ PHI=.75 LAMBDA=1.87M RD=28.2 RS=145.2 IS=31.2F PB=.8 MJ=.46
+ CBD=47.6P CBS=57.2P CGSO=70.2N CGDO=58.5N CGBO=96.3N)
.ENDS 4069UB
*$
*
*************

In LTSPICE

Version 4
SHEET 1 1240 680
WIRE 144 160 96 160
WIRE 96 160 96 288
WIRE 96 432 144 432
WIRE 192 352 192 288
WIRE 192 144 192 112
WIRE 192 448 192 480
WIRE 96 288 48 288
WIRE 96 288 96 432
WIRE 192 288 240 288
WIRE 192 288 192 240
FLAG 192 112 VDD
IOPIN 192 112 In
FLAG 192 480 VDD
IOPIN 192 480 In
FLAG 48 288 IN
IOPIN 48 288 In
FLAG 240 288 OUT
IOPIN 240 288 Out
SYMBOL nmos 144 352 R0
WINDOW 0 57 39 Left 0
WINDOW 3 58 60 Left 0
SYMATTR InstName M2
SYMATTR Value CD4069BN
SYMBOL pmos 144 240 M180
WINDOW 0 60 59 Left 0
WINDOW 3 59 34 Left 0
SYMATTR InstName M1
SYMATTR Value CD4069BP
TEXT 336 232 Left 0 !.MODEL CD4069BN NMOS (LEVEL=1 VTO=2.1 KP=2.9M
GAMMA=3.97U\n+ PHI=.75 LAMBDA=1.87M RD=20.2 RS=184.1 IS=31.2F PB=.8
MJ=.46\n+ CBD=47.6P CBS=57.2P CGSO=70.2N CGDO=58.5N CGBO=96.3N)\n.MODEL
CD4069BP PMOS (LEVEL=1 VTO=-2.9 KP=2M GAMMA=3.97U\n+ PHI=.75
LAMBDA=1.87M
RD=28.2 RS=145.2 IS=31.2F PB=.8 MJ=.46\n+ CBD=47.6P CBS=57.2P CGSO=70.2N
CGDO=58.5N CGBO=96.3N)

OK, it's a bit of a hack but someone else might tidy it up.

DNA

Aha! Looks promising... now what do I do with that bit of text to make
a component model with it? I'm putting the circuit in using circuit
piccies, not using a netlist.

Thanks, NT

You copy the text into notepad and then save the file with a .asc extension.
LTspice will then open it up as a schematic.

DNA

Kevin Aylward · Nov 19, 2004

Jim Thompson wrote:

On Thu, 18 Nov 2004 13:54:40 -0500, Keith Williams <krw@att.bizzzz
wrote:

In article <8qkpp0hjhr7qklj41ttnjoqhc6m543sn4i@4ax.com>,
thegreatone@example.com says...
On Thu, 18 Nov 2004 11:11:38 -0500, Keith Williams <krw@att.bizzzz
wrote:

In article <uffpp0p7i7gqq1v8u7jj0ki9ffbfdba78r@4ax.com>,
thegreatone@example.com says...
[snip]

As for worst case, I don't do Monte Carlo, because, in an IC,
components of a given type don't wander relative to each other.

Sure they do, with the added complication of device tracking.

Device tracking problems are only an issue with amateur designers
;-)

Tracking problems don't exist? You must live in a charmed world of
perfection. However, I must say that I no longer do circuit design,
so... ;-)

Devices that are located a few microns apart DO tend to track...
designers who rely on tracking cross-chip are fools ;-)

Yes, but devices, even x-coupled next to each other still have matching
errors. In some applications, you have to make the devices pretty big to
get the desired accuracy. For example, a small mos next to another will
be pushing it to match better than 1%. Getting a Vt match of 1mV is very
difficult for many processes. So, yes, there are amateur designers that
think close devices match to 0% error, and don't bother checking with
Monty Carlo, or otherwise

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

Joerg · Nov 19, 2004

Hi Kevin,

Yes, but devices, even x-coupled next to each other still have matching
errors. In some applications, you have to make the devices pretty big to
get the desired accuracy. For example, a small mos next to another will
be pushing it to match better than 1%. Getting a Vt match of 1mV is very
difficult for many processes. So, yes, there are amateur designers that
think close devices match to 0% error, and don't bother checking with
Monty Carlo, or otherwise

Another issue that younger designers often overlook is that orientation
can really matter even if the devices are very close to each other.

I don't like Monte Carlo for chip checks and balances, simulating with
process extremes is what I'd consider and I guess that is what Jim said.
Actually I also do the extreme scenario on discrete designs. But I do
like "Monty Carlo"

Regards, Joerg

http://www.analogconsultants.com

Jim Thompson · Nov 19, 2004

On Fri, 19 Nov 2004 18:15:01 GMT, Joerg
<notthisjoergsch@removethispacbell.net> wrote:

Hi Kevin,

Yes, but devices, even x-coupled next to each other still have matching
errors. In some applications, you have to make the devices pretty big to
get the desired accuracy. For example, a small mos next to another will
be pushing it to match better than 1%. Getting a Vt match of 1mV is very
difficult for many processes. So, yes, there are amateur designers that
think close devices match to 0% error, and don't bother checking with
Monty Carlo, or otherwise

Another issue that younger designers often overlook is that orientation
can really matter even if the devices are very close to each other.

I don't like Monte Carlo for chip checks and balances, simulating with
process extremes is what I'd consider and I guess that is what Jim said.
Actually I also do the extreme scenario on discrete designs. But I do
like "Monty Carlo"

Regards, Joerg

http://www.analogconsultants.com

480)460-2350 | |
| E-mail Address at Website Fax

Kevin Aylward · Nov 19, 2004

Joerg wrote:

Hi Kevin,

Yes, but devices, even x-coupled next to each other still have
matching errors. In some applications, you have to make the devices
pretty big to get the desired accuracy. For example, a small mos
next to another will be pushing it to match better than 1%. Getting
a Vt match of 1mV is very difficult for many processes. So, yes,
there are amateur designers that think close devices match to 0%
error, and don't bother checking with Monty Carlo, or otherwise

Another issue that younger designers often overlook is that
orientation can really matter even if the devices are very close to
each other.

I don't like Monte Carlo for chip checks and balances,

I agree, in that in reality, I dont do MC on a chip design, although I
have run 10,000's of WC.

simulating with
process extremes is what I'd consider

But one should still note that the process extremes don't necessarily
give you the max/min voltages and currents.

and I guess that is what Jim
said.

But what one also needs to do at key points is to actually manually
mismatch the W or L in say, a diff pair and put in voltage offsets.
Typical WC runs makes it all max or min, which dose nothing for the
checking the effect of basic offsets.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

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