signals of record

hi guys... new to vhdl here. Want to know how to make the signals in a
record on the ports of an entity.

type myrecord is record
a : ...
b : ...
end record;

signal mysig : myrecord;

entity myentity is
port (
-- how to make mysig.a and mysig.b as in and out port
respectively??

)
end myentity;

 

[Mike Treseler]

yiipee@gmail.com wrote:

hi guys... new to vhdl here. Want to know how to make the signals in a
record on the ports of an entity.

http://groups.google.com/groups/?q=vhdl+record+port+direction

 

[Aiken]

You better separate in and out for each record
so all the input in one record type
and all the output in one record type

This will make your life easy.



On Sep 30, 4:53 pm, yii...@gmail.com wrote:

hi guys... new to vhdl here. Want to know how to make the signals in a
record on the ports of an entity.

type myrecord is record
   a : ...
   b : ...
end record;

signal mysig : myrecord;

entity myentity is
   port (
        -- how to make mysig.a and mysig.b as in and out port
respectively??

         )
   end myentity;

 

[KJ]

On Sep 30, 4:53 pm, yii...@gmail.com wrote:

hi guys... new to vhdl here. Want to know how to make the signals in a
record on the ports of an entity.

type myrecord is record
   a : ...
   b : ...
end record;

signal mysig : myrecord;

entity myentity is
   port (
        -- how to make mysig.a and mysig.b as in and out port
respectively??

         )
   end myentity;

You can't. A particular signal on an entity interfaces can only be of
one mode (i.e. 'in', 'out', 'inout', 'buffer'). Ways to accomplish
what you want:

1. Change 'myentity' to work with whatever type 'mysig.a' and
'mysig.b' are. This presumes though that 'myentity' doesn't need
other stuff from the 'myrecord' type.

2. Split 'myrecord' into two types, one to handle 'inputs' the other
to handle 'outputs'. Sometimes this works but many times it doesn't
because there are then other entities that need connections to the
'outputs' because they use them as 'inputs'. The whole concept of
'in' and 'out' is always relative since the 'out' of one entity is
always the 'in' of another.

3. If the signals going in and out of 'myentity' are not simple types
(i.e. std_logic_vector, integer, etc.) so that #1 doesn't apply, then
restructure the I/O into records that are specific to 'myentity'. In
a sense this is very similar to #2 in that you'll have multiple
records (ones for the inputs to 'myentity' and a separate one for the
outputs). The difference is that you're working from the bottom up,
if there are other entities that will be working with certain sub-
elements, they would have their own record types defined. The thing
that then instantiates 'myentity' (and any other entities) will have
to then work directly with these two record types. Whether you find
it useful at that level to combine them as elements of yet another
record type (as shown below) is up to you while you're working on that
level of the design (many times it's not).

--- Sample pseudo code
entity myentity is
port (
abc : in t_gazintas;
def : out t_gazoutas
);

-- One way to instantiate...
signal abc : t_gazintas;
signal def : t_gazoutas
....
The_Thing : entity work.myentity
port map(
abc => abc,
def => def
);

-- Another way to instantiate...
type t_blob is record
abc : t_gazintas;
def : t_gazoutas
end record;
signal zblob: t_blob;
....
The_Thing : entity work.myentity
port map(
abc => zblob.abc,
def => zblob.def
);

Kevin Jennings

 

[Andy]

On Sep 30, 8:04 pm, Aiken <aikenp...@gmail.com> wrote:

You better separate in and out for each record
so all the input in one record type
and all the output in one record type

This will make your life easy.

On Sep 30, 4:53 pm, yii...@gmail.com wrote:

hi guys... new to vhdl here. Want to know how to make the signals in a
record on the ports of an entity.

type myrecord is record
   a : ...
   b : ...
end record;

signal mysig : myrecord;

entity myentity is
   port (
        -- how to make mysig.a and mysig.b as in and out port
respectively??

         )
   end myentity;

Actually it usually does not help much, since different ends of that
record require different subsets of ins, outs and inouts for the same
group of signals (think of master vs slave interfaces on a bus).

Almost as ugly is to declare the port as inout, use resolved types
(SL, SLV, unsigned, etc.) in the record definition, and then add
default 'Z' drivers for those elements where they are really only used
as inputs. You can also just define a constant of all 'Z's for the
record type and include a default assignment with that for any process
that drives any part of the record. Ugly, yes, but it works until the
language gods answer our prayers for a user defined mode for record
types.

I wonder if the guarded signal assignment facility would work and be
more efficient to simulate than all those resolved signals? One other
drawback of the inout method with resolved signals is that simulations
take longer, since everything has multiple drivers that have to be
resolved.

Andy