SiC fet gate damage...

[whit3rd]

On Tuesday, September 26, 2023 at 9:53:44 AM UTC-7, John Larkin wrote:

On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:

On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com
wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.


I have experience with Rohm SiC FETs. These were -4V maximum negative
voltage for those gen 3 (I think) parts.

They do NOT like being over-biased negatively. I think everybody\'s
SiC FETs don\'t like too much negative voltage.

I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.

My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.

boB

Right. I want to run the Cree gates at +15 and -5, and the upper fet
source pulses to +500, so I have to be careful that there is no case
where I over-voltage the gate in either direction. I want speed, and
zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.

SiC fets are hard to drive but otherwise great.

A non-simple zener clamp would bias the zeners and use switch diodes
to those (the switch diode having presumably lower capacitance).
Switch diodes have low cost, both money and capacitance.

 

[John Larkin]

On Wed, 27 Sep 2023 17:30:16 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

On Tuesday, September 26, 2023 at 9:53:44?AM UTC-7, John Larkin wrote:
On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:

On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com
wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.


I have experience with Rohm SiC FETs. These were -4V maximum negative
voltage for those gen 3 (I think) parts.

They do NOT like being over-biased negatively. I think everybody\'s
SiC FETs don\'t like too much negative voltage.

I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.

My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.

boB

Right. I want to run the Cree gates at +15 and -5, and the upper fet
source pulses to +500, so I have to be careful that there is no case
where I over-voltage the gate in either direction. I want speed, and
zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.

SiC fets are hard to drive but otherwise great.

A non-simple zener clamp would bias the zeners and use switch diodes
to those (the switch diode having presumably lower capacitance).
Switch diodes have low cost, both money and capacitance.

The series LM4040 is paralleled with a capacitor, so its capacitance
doesn\'t matter.