SiC fet gate damage...

[John Larkin]

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

 

[Phil Hobbs]

John Larkin <jl@997PotHill.com> wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

I have an app note from EPC that says that the gates are pretty delicate.
Since the gate is in contact with the 2DEG, I’d expect it to be very
vulnerable to hot-carrier damage.

I’ll try to dig out the app note.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC /
Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

 

[Lasse Langwadt Christensen]

something in this? https://www.mdpi.com/2075-1702/10/12/1194

 

[John Larkin]

On Mon, 25 Sep 2023 20:02:38 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

John Larkin <jl@997PotHill.com> wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.



I have an app note from EPC that says that the gates are pretty delicate.
Since the gate is in contact with the 2DEG, I’d expect it to be very
vulnerable to hot-carrier damage.

I’ll try to dig out the app note.

Cheers

Phil Hobbs

I don\'t have a lot of these handy so I don\'t want to fry many.

A quick test was to apply -v to the gate through 10K. Up to -30 volts,
leakage was tiny, sub-uA probably. About -40, it started clipping. At
around 1 mA, it died hard.

I\'m considering a UCC21520 half-bridge driver, but these SiC things
like negative gate bias, -5 maybe, so I need to add some offset, but
never too much. Series zener and some sort of pulldown is safe. The
high side fet source will swing to +500!

 

[John Larkin]

On Mon, 25 Sep 2023 20:02:38 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

John Larkin <jl@997PotHill.com> wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.



I have an app note from EPC that says that the gates are pretty delicate.
Since the gate is in contact with the 2DEG, I’d expect it to be very
vulnerable to hot-carrier damage.

I’ll try to dig out the app note.

Cheers

Phil Hobbs

This should work:

https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1

The LM4040 only needs 60 uA, and duty cycle will be low, so we
probably won\'t fry R1+R2 when they have 500 volts across them.

R1/R2 could be a bit bigger.

I was thinking about a fancy depletion fet for the pulldown, but
resistors should work.

Those half-bridge drivers are amazing. That one has 5.7 KV isolation.
Can that be one chip?

 

[boB]

On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <jl@997PotHill.com>
wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

I have experience with Rohm SiC FETs. These were -4V maximum negative
voltage for those gen 3 (I think) parts.

They do NOT like being over-biased negatively. I think everybody\'s
SiC FETs don\'t like too much negative voltage.

I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.

My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.

boB

 

[John Larkin]

On Tue, 26 Sep 2023 09:15:13 -0700, boB <boB@K7IQ.com> wrote:

On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <jl@997PotHill.com
wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.


I have experience with Rohm SiC FETs. These were -4V maximum negative
voltage for those gen 3 (I think) parts.

They do NOT like being over-biased negatively. I think everybody\'s
SiC FETs don\'t like too much negative voltage.

I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.

My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.

boB

Right. I want to run the Cree gates at +15 and -5, and the upper fet
source pulses to +500, so I have to be careful that there is no case
where I over-voltage the gate in either direction. I want speed, and
zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.

SiC fets are hard to drive but otherwise great.

 

[Lasse Langwadt Christensen]

tirsdag den 26. september 2023 kl. 18.53.44 UTC+2 skrev John Larkin:

On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:

On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com
wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.


I have experience with Rohm SiC FETs. These were -4V maximum negative
voltage for those gen 3 (I think) parts.

They do NOT like being over-biased negatively. I think everybody\'s
SiC FETs don\'t like too much negative voltage.

I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.

My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.

boB

Right. I want to run the Cree gates at +15 and -5, and the upper fet
source pulses to +500, so I have to be careful that there is no case
where I over-voltage the gate in either direction. I want speed, and
zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.

plenty with <1pf and ~5Vbr , https://www.onsemi.com/products/discrete-power-modules/esd-protection-diodes

 

[John Smiht]

On Tuesday, September 26, 2023 at 1:13:50 PM UTC-5, Lasse Langwadt Christensen wrote:

tirsdag den 26. september 2023 kl. 18.53.44 UTC+2 skrev John Larkin:
On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:

On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com
wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.


I have experience with Rohm SiC FETs. These were -4V maximum negative
voltage for those gen 3 (I think) parts.

They do NOT like being over-biased negatively. I think everybody\'s
SiC FETs don\'t like too much negative voltage.

I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.

My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.

boB

Right. I want to run the Cree gates at +15 and -5, and the upper fet
source pulses to +500, so I have to be careful that there is no case
where I over-voltage the gate in either direction. I want speed, and
zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.
plenty with <1pf and ~5Vbr , https://www.onsemi.com/products/discrete-power-modules/esd-protection-diodes

Thanks, Lasse, for the great link. Much appreciated.
John

 

[John Larkin]

On Tue, 26 Sep 2023 11:13:45 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

tirsdag den 26. september 2023 kl. 18.53.44 UTC+2 skrev John Larkin:
On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:

On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com
wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.


I have experience with Rohm SiC FETs. These were -4V maximum negative
voltage for those gen 3 (I think) parts.

They do NOT like being over-biased negatively. I think everybody\'s
SiC FETs don\'t like too much negative voltage.

I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.

My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.

boB

Right. I want to run the Cree gates at +15 and -5, and the upper fet
source pulses to +500, so I have to be careful that there is no case
where I over-voltage the gate in either direction. I want speed, and
zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.

plenty with <1pf and ~5Vbr , https://www.onsemi.com/products/discrete-power-modules/esd-protection-diodes

The thing I posted above

https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1

looks safe. I can make the -10 into -24, which helps.

 

[amal banerjee]

On Monday, September 25, 2023 at 10:37:25 PM UTC+5:30, John Larkin wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

Please check out:
https://www.powerelectronicsnews.com/how-to-select-the-right-gate-driver-for-your-sic-mosfet/
Also if you use the search string \"SiC FET gate driver\" on Google, a list of semiconductor device
manufacturers(notably Infinieon, TI etc.,) is shown, which have whole sets of gate driver ICs for both
SiC and GaN power FETs.

 

[John Larkin]

On Tue, 26 Sep 2023 23:55:26 -0700 (PDT), amal banerjee
<dakupoto@gmail.com> wrote:

On Monday, September 25, 2023 at 10:37:25?PM UTC+5:30, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.
Please check out:
https://www.powerelectronicsnews.com/how-to-select-the-right-gate-driver-for-your-sic-mosfet/
Also if you use the search string \"SiC FET gate driver\" on Google, a list of semiconductor device
manufacturers(notably Infinieon, TI etc.,) is shown, which have whole sets of gate driver ICs for both
SiC and GaN power FETs.

One market for SiC fets is as high power IGBT replacements, where
speed and especially insertion delay don\'t much matter. Those gate
drivers are super slow, sometimes hundreds of ns delay.

I want speed. The UCC21520 is pretty fast, both prop delay and edge
rates into a modest-sized SiC fet.

I could go faster with a home-made driver, but shouldn\'t need to go to
that much trouble to save a few ns.

One problem with SiC fets is that, compared to silicon mosfets, they
have high internal gate resistances. Swinging negative on the gate
drive slams them through their threshold voltage and helps them turn
off faster. They don\'t need negative swing otherwise.

GaN is great to drive. The EPC parts can be driven unipolar from a
cheap TinyLogic cmos gate. That in turn can make a good SiC gate
drive. Fast and complex.

The volume markets for GaN and SiC are power and RF.

 

[Fred Bloggs]

On Monday, September 25, 2023 at 1:07:25 PM UTC-4, John Larkin wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

Use another SiC to clamp that gate drive to a safe level.

 

[Fred Bloggs]

On Monday, September 25, 2023 at 1:07:25 PM UTC-4, John Larkin wrote:

Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

What does your gate driver look like? Maybe you just need better decoupling..

 

[John Larkin]

On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

What does your gate driver look like? Maybe you just need better decoupling.

This looks pretty good:

https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1

If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.

 

[Piglet]

On 27/09/2023 15:55, John Larkin wrote:

On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
bloggs.fredbloggs.fred@gmail.com> wrote:

On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

What does your gate driver look like? Maybe you just need better decoupling.

This looks pretty good:

https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1

If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.

Or use BSS126 / LND150 as pulldowns?

piglet

 

[Fred Bloggs]

On Wednesday, September 27, 2023 at 10:56:15 AM UTC-4, John Larkin wrote:

On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
bloggs.fred...@gmail.com> wrote:
On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

What does your gate driver look like? Maybe you just need better decoupling.
This looks pretty good:

https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1

If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.

Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time.

That UCC5120 is powerful. I\'m surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC\'s take though.

 

[Piglet]

On 27/09/2023 17:27, Fred Bloggs wrote:

On Wednesday, September 27, 2023 at 10:56:15 AM UTC-4, John Larkin wrote:
On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
bloggs.fred...@gmail.com> wrote:
On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

What does your gate driver look like? Maybe you just need better decoupling.
This looks pretty good:

https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1

If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.

Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time.

That UCC5120 is powerful. I\'m surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC\'s take though.

What (?little) abuse there might be will most likely be borne by the 1uF
rather than the LM4040?

piglet

 

[John Larkin]

On Wed, 27 Sep 2023 16:43:38 +0100, Piglet <erichpwagner@hotmail.com>
wrote:

On 27/09/2023 15:55, John Larkin wrote:
On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
bloggs.fredbloggs.fred@gmail.com> wrote:

On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

What does your gate driver look like? Maybe you just need better decoupling.

This looks pretty good:

https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1

If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.





Or use BSS126 / LND150 as pulldowns?

piglet

Yes, I use LND150 a lot, but two resistors is easy with no dynamic
concerns.

The Cree fet has pA DC gate currents over its specified gate voltage
range. pA drain current, too, at zero gate bias! So I only need 60 uA
to keep the 4040 alive.

 

[John Larkin]

On Wed, 27 Sep 2023 09:27:08 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

On Wednesday, September 27, 2023 at 10:56:15?AM UTC-4, John Larkin wrote:
On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
bloggs.fred...@gmail.com> wrote:
On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?

Specifically, I\'m designing a gate driver for the Cree C2M0280120D and
I\'m wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.

I\'ll get some from stock later and test some, but that\'s necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.

googling hasn\'t helped.

What does your gate driver look like? Maybe you just need better decoupling.
This looks pretty good:

https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1

If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.

Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time.

Fall time comes from the amps of drive from the TI chip. The resistive
pulldown can be a hundred uA or so.

That UCC5120 is powerful. I\'m surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC\'s take though.

The 4040 will only see the tiny DC bias current.