Should VHDL allow Unicode identifiers and comments

[Martin Thompson]

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
a) Something VHDL should not allow
b) Something that doesn't bother you either way
c) Something you'd find useful sometimes
d) Something you'd make use of all the time
e) Something that you'd switch away from SystemVerilog just to get at
(maybe I'm asking the wrong crowd for that

Thanks,
Martin

--
http://parallelpoints.com/

 

[Christopher Felton]

On 7/28/2011 2:13 PM, Martin Thompson wrote:

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
a) Something VHDL should not allow
b) Something that doesn't bother you either way
c) Something you'd find useful sometimes
d) Something you'd make use of all the time
e) Something that you'd switch away from SystemVerilog just to get at
(maybe I'm asking the wrong crowd for that

Thanks,
Martin

b,

Regards,
Chris Fetlon

 

[Rob Gaddi]

On 7/28/2011 2:10 PM, Christopher Felton wrote:

On 7/28/2011 2:13 PM, Martin Thompson wrote:
Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
a) Something VHDL should not allow
b) Something that doesn't bother you either way
c) Something you'd find useful sometimes
d) Something you'd make use of all the time
e) Something that you'd switch away from SystemVerilog just to get at
(maybe I'm asking the wrong crowd for that

Thanks,
Martin


b,

Regards,
Chris Fetlon

Unless the introduction of said identifiers started breaking my existing
tools, in which case (a).

--
Rob Gaddi, Highland Technology
Email address is currently out of order

 

[Mike Treseler]

On 7/28/2011 12:13 PM, Martin Thompson wrote:

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
a) Something VHDL should not allow
b) Something that doesn't bother you either way
c) Something you'd find useful sometimes

c) Yes, will be helpful in the near future.
Otherwise everyone will have a different library for it.

d) Something you'd make use of all the time
e) Something that you'd switch away from SystemVerilog just to get at
(maybe I'm asking the wrong crowd for that

Thanks,
Martin

 

[Martin Thompson]

Mike Treseler <mtreseler@gmail.com> writes:

c) Something you'd find useful sometimes

c) Yes, will be helpful in the near future.
Otherwise everyone will have a different library for it.

I'm not sure I follow Mike - library for what? The original question
was about using Unicode within a VHDL source file (for example, variable
names and comments).

Or are you thinking of having a Unicode "string" replacement - which is
a whole different ballgame, but one we maybe ought to think of also!

Cheers,
Martin

 

[Mike Treseler]

On 7/29/2011 2:55 AM, Martin Thompson wrote:

Mike Treseler<mtreseler@gmail.com> writes:

c) Something you'd find useful sometimes

c) Yes, will be helpful in the near future.
Otherwise everyone will have a different library for it.


I'm not sure I follow Mike - library for what? The original question
was about using Unicode within a VHDL source file (for example, variable
names and comments).

OK. In that case probably (b) for English speakers.

Or are you thinking of having a Unicode "string" replacement - which is
a whole different ballgame, but one we maybe ought to think of also!

Yes, I was thinking strings.
That seems safe and probably useful.
Programming languages without
Unicode strings built-in suffer as a result.


-- Mike Treseler

 

[Jonathan Bromley]

On 28 Jul 2011 19:13:48 GMT, Martin Thompson
<martin_usenet@parallelpoints.com> wrote:

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

I'm not sure I see any use for it. What do you have in mind?

Unicode *strings* and file-IO might well be useful, but
I guess that's a very different story. A new type, either
built-in or in std.standard, for Unicode *characters* would
be a good start.
--
Jonathan Bromley

 

[Martin Thompson]

Jonathan Bromley <spam@oxfordbromley.plus.com> writes:

On 28 Jul 2011 19:13:48 GMT, Martin Thompson
martin_usenet@parallelpoints.com> wrote:

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

I'm not sure I see any use for it. What do you have in mind?

The original question was asked without much in mind beyond allowing you
to call a variable 'château' (to pull an example from the other end of
the scale spectrum to our usual fare here

Unicode *strings* and file-IO might well be useful, but
I guess that's a very different story. A new type, either
built-in or in std.standard, for Unicode *characters* would
be a good start.

From other comments, Unicode strings appear to be of much more value
than Unicode identifiers and comments. Although once you allow Unicode
strings in a source file, you've opened the "source-file encoding" can
of worms already, and then (I believe) allowing Unicode in comments
becomes easy. Unicode identifiers may have some negative impact of
parsing efficiency?

In which case, as you say, W_CHARACTER here we (might) come. However,
it also sounds like a large (huge?) amount of work which *may* be better
spent elsewhere.

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[Jonathan Bromley]

On Mon, 01 Aug 2011 09:58:21 +0100, Martin Thompson wrote:

The original question was asked without much in mind beyond
allowing you to call a variable 'château'

C'est tout possible de faire son logiciel sans aucun accent

it also sounds like a large (huge?) amount of work which
*may* be better spent elsewhere.

I think I tend to agree. The EDA industry as a whole is
irremediably Anglophone, and muddles through pretty well
without internationalization.
--
Jonathan Bromley

 

[Martin Thompson]

Jonathan Bromley <spam@oxfordbromley.plus.com> writes:

The EDA industry as a whole is
irremediably Anglophone,

I like that description

and muddles through pretty well
without internationalization.

and likely will continue to do so!

Thanks,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[Anssi Saari]

Martin Thompson <martin_usenet@parallelpoints.com> writes:

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
c) Something you'd find useful sometimes

I liked an example snippet in Python I saw some time ago. There's
another one at
http://programmers.stackexchange.com/questions/16010/is-it-bad-to-use-unicode-characters-in-variable-names

for example.

After all, if your angle is phi, then why bother writing it out when
you can just use 'φ' instead?

 

After all, if your angle is phi, then why bother writing it out when
you can just use 'φ' instead?

I like that example. I prefer to write math equations using symbols too, rather than typing in 'English'. Sometimes, greek is better than english when it comes to math/physics... IMO.

I may not be answering the question, but I will vote:
f) something that the VHDL standard shouldn't be concerned about.

Let the tool vendors concern themselves on this when they have enough customer demand. I believe I won't face much problems when I'm using two different vendor tools (say for synthesis and simulation) who both claim to be Unicode-compliant.

 

[Daniel Leu]

On Thursday, July 28, 2011 12:13:48 PM UTC-7, Martin Thompson wrote:

Hi all,

I'm asking for a bit of input from the community...

As the title says, would you find it of use to allow Unicode identifiers
and comments in a future VHDL revision?

Would this be:
a) Something VHDL should not allow
b) Something that doesn't bother you either way
c) Something you'd find useful sometimes
d) Something you'd make use of all the time
e) Something that you'd switch away from SystemVerilog just to get at
(maybe I'm asking the wrong crowd for that

Thanks,
Martin

--
http://parallelpoints.com/

a) Something VHDL should not allow

Comments would be fine. I am more worried about the entire toolchain: netlist representation, p&r tools, graphical visualization.


- Daniel