S-R latch

[sophia]

Hi ,

the following is the implementation of S-R latch which i saw in a
book,

http://i297.photobucket.com/albums/mm220/sophiaagnes/Scan3.jpg

and the following is the truth table based on it
http://i297.photobucket.com/albums/mm220/sophiaagnes/scan2.jpg


now in the book it is written that when both s & R are made high
simultaneously both the o/p will be low
and the value of Q is unpredictable (1 or 0) depending on the
circuit condition

now my question is what is this circuit condition that Q depends on ?

 

[John Fields]

On Fri, 1 Aug 2008 03:29:48 -0700 (PDT), sophia
<sophia.agnes@gmail.com> wrote:

Hi ,

the following is the implementation of S-R latch which i saw in a
book,

http://i297.photobucket.com/albums/mm220/sophiaagnes/Scan3.jpg

and the following is the truth table based on it
http://i297.photobucket.com/albums/mm220/sophiaagnes/scan2.jpg


now in the book it is written that when both s & R are made high
simultaneously both the o/p will be low
and the value of Q is unpredictable (1 or 0) depending on the
circuit condition

now my question is what is this circuit condition that Q depends on ?

---
Assuming that S and R are both high and then go low simultaneously,
the gate with the shortest input-to-output delay will force the output
of the other gate low.

JF

 

[John Popelish]

sophia wrote:

Hi ,

the following is the implementation of S-R latch which i saw in a
book,

http://i297.photobucket.com/albums/mm220/sophiaagnes/Scan3.jpg

and the following is the truth table based on it
http://i297.photobucket.com/albums/mm220/sophiaagnes/scan2.jpg


now in the book it is written that when both s & R are made high
simultaneously both the o/p will be low

It is not important that they go high simultaneously, only
that they *be* high at the same time, since a NOR gate must
output a low if either if its inputs is high. So both the S
and R force their gates to a low when these signals are
high, over riding the cross connections.

and the value of Q is unpredictable (1 or 0) depending on the
circuit condition

now my question is what is this circuit condition that Q depends on ?

It is called a race condition, when both S and R go low at
the same time. At that moment, both gates have two low
inputs, one from the just transitioned S or R going low, and
one from the most recent forced low output from the other
gate. That means both gated head toward a high output and
the one that gets there first will force the output of the
other back to a low. The circuit conditions involve
anything that affects the speed (propagation delay) of each
gate, like temperature, transistor gain differences,
resistor tolerances, wire lengths, etc.

The more closely matched the two gates are, the longer it
takes for the race condition to be resolved into a winner
and a loser.

Circuit simulations of such a thing, where both gates and
their signals can be mathematically identical to many
decimal places, can oscillate for many cycles before the
race is decided.

--
Regards,

John Popelish