Ring counters, again!

[George Herold]

On Wednesday, September 25, 2019 at 5:25:34 PM UTC-4, bitrex wrote:

On 9/25/19 3:24 PM, George Herold wrote:

Why not just use a counter/ divider '4017 or '4022?
https://www.ti.com/lit/ds/symlink/cd4017b.pdf

George H.


4000 series are too slow at low voltage at the speed I need to go at.
What voltage? 74HC4017?

GH

1.8, idk if there are any appropriate Johnson counter in the 74LVC series.

1.8V ! and some opamp filtering? how about a little boost thingie?

George H.

 

[whit3rd]

On Wednesday, September 25, 2019 at 7:47:32 AM UTC-7, Rick C wrote:

On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The use of a ganged flipflop (all clocked together) basically
solves the race and (if there's a Schmitt trigger clock) glitching problem.
The CD4022, however, is a ripple counter (not synchronous) so will
work, but have relatively sloppy timing.

 

[Rick C]

On Thursday, September 26, 2019 at 2:46:49 AM UTC-4, whit3rd wrote:

On Wednesday, September 25, 2019 at 7:47:32 AM UTC-7, Rick C wrote:
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The use of a ganged flipflop (all clocked together) basically
solves the race and (if there's a Schmitt trigger clock) glitching problem.
The CD4022, however, is a ripple counter (not synchronous) so will
work, but have relatively sloppy timing.

Not sure how you think multiple outputs can change simultaneously without producing glitches in a DAC circuit. The problem can be reduced to a desired accuracy by various means, but it can not be solved systematically.

If you have multiple outputs changing at once, a DAC will always have glitching problems. The only issue is whether the glitches can be reduced enough to be acceptable.

If this were being done on a single die it would be feasible to use the output of the decoder to enable 1 of N analog switches connecting the output to the elements of a resistor ladder designed to produce a sine wave. But that is far too much logic for this simple effort using discrete devices.

--

Rick C.

-+ Get 2,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Thursday, September 26, 2019 at 1:45:47 PM UTC-4, whit3rd wrote:

On Thursday, September 26, 2019 at 6:37:18 AM UTC-7, Rick C wrote:
On Thursday, September 26, 2019 at 2:46:49 AM UTC-4, whit3rd wrote:

If you have multiple outputs changing at once, a DAC will always have glitching problems. The only issue is whether the glitches can be reduced enough to be acceptable.

In the example case here, the slewing of multiple CMOS outputs is the analog output (summed
with a resistor network). So as long as the slew is similar in all sections, the output value
will evolve linearly in time, making a smooth transition from one state to the next.
I'd regard the section-to-section variations on a chip as a very minor concern.

A clock glitch, however, could be more dramatic, up to and including metastable
oscillations.

I'm not sure where you are getting your info. First, the CD4022 does not contain a ripple counter. It contains a Johnson ring counter. The outputs are decoded, glitch free, using two input AND gates which detect the edge of the state bit values.

https://www.futurlec.com/Datasheet/CD4000/CD4022.pdf

Page 6 shows the schematic.

Then this same data sheet shows the propagation delays from clock to output to be much longer than the transition times, 2:1 for the rising edge and 4:1 for the falling edge. So it is entirely possible for the variation of propagation time to be very significant compared to the slew rate of the outputs.

Using the CD4022 for a sine wave generator provides no significant advantages over a shift register other than not needing the inverter. It does require twice as many resistors and connections and may have glitches at the transitions due to two signals changing at the same time. The glitching issue may not be an issue at 200 kHz, but at faster rates the glitches will be more prominent. It's not just a matter of section to section variation, but rising edge vs. falling edge effects.

So, the CD4022 has potential problems vs. no advantages.

--

Rick C.

+- Get 2,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[whit3rd]

On Thursday, September 26, 2019 at 6:37:18 AM UTC-7, Rick C wrote:

On Thursday, September 26, 2019 at 2:46:49 AM UTC-4, whit3rd wrote:

If you have multiple outputs changing at once, a DAC will always have glitching problems. The only issue is whether the glitches can be reduced enough to be acceptable.

In the example case here, the slewing of multiple CMOS outputs is the analog output (summed
with a resistor network). So as long as the slew is similar in all sections, the output value
will evolve linearly in time, making a smooth transition from one state to the next.
I'd regard the section-to-section variations on a chip as a very minor concern.

A clock glitch, however, could be more dramatic, up to and including metastable
oscillations.

 

[Rick C]

On Thursday, September 26, 2019 at 5:09:19 PM UTC-4, whit3rd wrote:

On Thursday, September 26, 2019 at 11:19:01 AM UTC-7, Rick C wrote:

I'm not sure where you are getting your info. First, the CD4022 does not contain a ripple counter. It contains a Johnson ring counter. The outputs are decoded, glitch free, using two input AND gates which detect the edge of the state bit values.

https://www.futurlec.com/Datasheet/CD4000/CD4022.pdf

There's variations; the CD4022 datasheet from RCA had gating delays AFTER the
flip-flops, the outputs wouldn't be synchronous even though the flip-flops were buffered.

The NatSemi datasheet does indeed show a better solution, timing-wise. It also omits the
Schmitt-trigger clock buffer, which makes setup/hold glitching somewhat more likely.

I found an RCA data sheet and the logic is identical. They ALL have delays after the FFs because the outputs are DECODED. But I don't know what you thought you saw in the RCA data sheet, they are all the same logic.

--

Rick C.

++ Get 2,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

 

[whit3rd]

On Thursday, September 26, 2019 at 11:19:01 AM UTC-7, Rick C wrote:

I'm not sure where you are getting your info. First, the CD4022 does not contain a ripple counter. It contains a Johnson ring counter. The outputs are decoded, glitch free, using two input AND gates which detect the edge of the state bit values.

https://www.futurlec.com/Datasheet/CD4000/CD4022.pdf

There's variations; the CD4022 datasheet from RCA had gating delays AFTER the
flip-flops, the outputs wouldn't be synchronous even though the flip-flops were buffered.

The NatSemi datasheet does indeed show a better solution, timing-wise. It also omits the
Schmitt-trigger clock buffer, which makes setup/hold glitching somewhat more likely.

 

[whit3rd]

On Thursday, September 26, 2019 at 2:33:08 PM UTC-7, Rick C wrote:

On Thursday, September 26, 2019 at 5:09:19 PM UTC-4, whit3rd wrote:
On Thursday, September 26, 2019 at 11:19:01 AM UTC-7, Rick C wrote:

I'm not sure where you are getting your info. First, the CD4022 does not contain a ripple counter. It contains a Johnson ring counter. The outputs are decoded, glitch free, using two input AND gates which detect the edge of the state bit values.

https://www.futurlec.com/Datasheet/CD4000/CD4022.pdf

There's variations; the CD4022 datasheet from RCA had gating delays AFTER the
flip-flops...

I found an RCA data sheet and the logic is identical. They ALL have delays after the FFs because the outputs are DECODED. But I don't know what you thought you saw in the RCA data sheet, they are all the same logic.

Reviewing it, you're right; two minor differences (Schmitt trigger in RCA, and three-input
gate in the National Semiconductor) but the Q-to-output pin delays should
all match, in both cases.

Still prefer the flipflop solution without decoder, because flipflop clock-to-output delay is
as regular as timing gets (independent of clock slew rate, for instance).

 

[Rick C]

On Friday, September 27, 2019 at 2:26:30 AM UTC-4, whit3rd wrote:

On Thursday, September 26, 2019 at 2:33:08 PM UTC-7, Rick C wrote:
On Thursday, September 26, 2019 at 5:09:19 PM UTC-4, whit3rd wrote:
On Thursday, September 26, 2019 at 11:19:01 AM UTC-7, Rick C wrote:

I'm not sure where you are getting your info. First, the CD4022 does not contain a ripple counter. It contains a Johnson ring counter. The outputs are decoded, glitch free, using two input AND gates which detect the edge of the state bit values.

https://www.futurlec.com/Datasheet/CD4000/CD4022.pdf

There's variations; the CD4022 datasheet from RCA had gating delays AFTER the
flip-flops...

I found an RCA data sheet and the logic is identical. They ALL have delays after the FFs because the outputs are DECODED. But I don't know what you thought you saw in the RCA data sheet, they are all the same logic.

Reviewing it, you're right; two minor differences (Schmitt trigger in RCA, and three-input
gate in the National Semiconductor) but the Q-to-output pin delays should
all match, in both cases.

Still prefer the flipflop solution without decoder, because flipflop clock-to-output delay is
as regular as timing gets (independent of clock slew rate, for instance).

That's why the Johnson ring counter is a good solution. No decoding required and only one output changes on each clock, so the inevitable asymmetries don't cause glitches.

--

Rick C.

--- Get 2,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209