Ring counters, again!

B

bitrex

Guest
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

<https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf>

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.
 
On 23.9.19 20:54, bitrex wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf


Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.
Click to expand...

For longer registers, there is a way to get the thing
back to the proper sequence by modifying the feedback
from the end.

1. Using wide AND gates to detect all ones and all zeroes
states and using them to turn a set-reset flip-flop which
then feeds the shift register serial input.

2. Using a counter to count to twice the shift register
length and using its most-significant bit to feed the
serial input.

--

-TV
 
On 9/23/19 2:21 PM, Tauno Voipio wrote:
On 23.9.19 20:54, bitrex wrote:
Incidentally, Bell Labs patented using a NOR gate to reject
dis-allowed states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf


Given that most D flops have not-Q that's all the patent is, a NOR
gate connected from two outputs to clear. for 20 years until 2005
you'd need to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed
walks is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.


For longer registers, there is a way to get the thing
back to the proper sequence by modifying the feedback
from the end.

1. Using wide AND gates to detect all ones and all zeroes
states and using them to turn a set-reset flip-flop which
then feeds the shift register serial input.

2. Using a counter to count to twice the shift register
length and using its most-significant bit to feed the
serial input.
Click to expand...

Ah, modify the feedback loop. that's the way to do it.
 
On Mon, 23 Sep 2019 13:54:05 -0400, bitrex <user@example.net> wrote:

Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.
Click to expand...

My FPGA guys say to set one bit at powerup, and trust that nothing
will ever go wrong.
 
On Monday, September 23, 2019 at 1:10:35 PM UTC-7, John Larkin wrote:
On Mon, 23 Sep 2019 13:54:05 -0400, bitrex <user@example.net> wrote:

Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

My FPGA guys say to set one bit at powerup, and trust that nothing
will ever go wrong.
Click to expand...

A wise man once said 'trust, but verify'. Anything with as many states as
a computer, should have a watchdog somewhere. I'm thinking most
finite-state-machine reasoning includes similarf wisdom.

An entire (DDR3) generation of memory has the rowhammer feature.
 
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.
Click to expand...

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
0000
1000
1100
1110
1111
0111
0011
0001

disalowed
0100
1010
1101
0110
1011
0101
0010
1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

--
When I tried casting out nines I made a hash of it.
 
On Monday, September 23, 2019 at 4:10:35 PM UTC-4, John Larkin wrote:
On Mon, 23 Sep 2019 13:54:05 -0400, bitrex <user@example.net> wrote:

Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.
Click to expand...

You can't detect these two states exclusively with a 4 input XOR. It's not as simple as you think. What you want to detect is that you have an edge in the chain. The presence of the edge and the state of the last FF determines the value fed back to the first FF. When there is one or no edge feedback the last FF inverted. When there is more than one edge feedback a zero. With only 4 FFs this is not too hard, but it's not a 4 input XOR. There are 16 possible states and only 8 are valid.

I don't know what might be optimal, you can do a Karnaugh map from the truth table to figure out that.


My FPGA guys say to set one bit at powerup, and trust that nothing
will ever go wrong.
Click to expand...

Set no bits at power up... it's called a reset. All zeros is a valid state in a Johnson ring counter. Detecting an invalid state in such a circuit would be at the high end of reliability, but not unheard of. Critical systems would want exactly that. In typical systems many other intermittent failures are much more likely.

--

Rick C.

- Get 2,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
 
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
0000
1000
1100
1110
1111
0111
0011
0001

disalowed
0100
1010
1101
0110
1011
0101
0010
1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.
Click to expand...

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The only practical, glitchless methods I know of for this use are the thermometer code or the Johnson ring counter. A grey code is glitchless, but I can't see a useful way to apply it here.

--

Rick C.

+ Get 2,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209
 
On 23/09/2019 21:10, John Larkin wrote:
On Mon, 23 Sep 2019 13:54:05 -0400, bitrex <user@example.net> wrote:


My FPGA guys say to set one bit at powerup, and trust that nothing
will ever go wrong.
Click to expand...

I'm glad I don't have a Larkin pacemaker fitted.
I suppose back-to-back monostables are just as good.
 
On 9/25/19 10:47 AM, Rick C wrote:
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
0000
1000
1100
1110
1111
0111
0011
0001

disalowed
0100
1010
1101
0110
1011
0101
0010
1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The only practical, glitchless methods I know of for this use are the thermometer code or the Johnson ring counter. A grey code is glitchless, but I can't see a useful way to apply it here.
Click to expand...

The main work of the patent above I think was the grunt work of proving
mathematically that that particular NOR gate connection can correct for
all possible erroneous states, in any length register, and can handle
all erroneous states, not just single bit-flip errors.

There are probably other logic configurations that will correct errors
for a particular counter, or perhaps even all counters, but if the
counter is too long to figure out if it works for all cases by
inspection one would have to "do the math."
 
On Wednesday, September 25, 2019 at 1:45:08 PM UTC-4, bitrex wrote:
On 9/25/19 10:47 AM, Rick C wrote:
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
0000
1000
1100
1110
1111
0111
0011
0001

disalowed
0100
1010
1101
0110
1011
0101
0010
1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The only practical, glitchless methods I know of for this use are the thermometer code or the Johnson ring counter. A grey code is glitchless, but I can't see a useful way to apply it here.


Integrated 4000-series Johnson counters are said to use this logic
between every 3rd flop stage to error-correct:

https://mysite.du.edu/~etuttle/electron/circ418.gif
Click to expand...

Why not just use a counter/ divider '4017 or '4022?
https://www.ti.com/lit/ds/symlink/cd4017b.pdf

George H.
 
On 9/25/19 10:47 AM, Rick C wrote:
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
0000
1000
1100
1110
1111
0111
0011
0001

disalowed
0100
1010
1101
0110
1011
0101
0010
1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The only practical, glitchless methods I know of for this use are the thermometer code or the Johnson ring counter. A grey code is glitchless, but I can't see a useful way to apply it here.
Click to expand...

Integrated 4000-series Johnson counters are said to use this logic
between every 3rd flop stage to error-correct:

<https://mysite.du.edu/~etuttle/electron/circ418.gif>
 
On Wednesday, September 25, 2019 at 2:40:21 PM UTC-4, George Herold wrote:
On Wednesday, September 25, 2019 at 1:45:08 PM UTC-4, bitrex wrote:
On 9/25/19 10:47 AM, Rick C wrote:
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
0000
1000
1100
1110
1111
0111
0011
0001

disalowed
0100
1010
1101
0110
1011
0101
0010
1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The only practical, glitchless methods I know of for this use are the thermometer code or the Johnson ring counter. A grey code is glitchless, but I can't see a useful way to apply it here.


Integrated 4000-series Johnson counters are said to use this logic
between every 3rd flop stage to error-correct:

https://mysite.du.edu/~etuttle/electron/circ418.gif

Why not just use a counter/ divider '4017 or '4022?
https://www.ti.com/lit/ds/symlink/cd4017b.pdf
Click to expand...

Because it will produce glitches in the output on every transition. The outputs don't change at the same time exactly. Maybe the timing is significant or maybe it's not. The ring counter has no glitches and is still a simple circuit with a good result. The prospect of disrupting the ring counter is not solved by using a binary counter. If the binary counter gets disrupted it also produces erroneous outputs. I suppose it is a short term disruption, but it isn't immune from the issue.

--

Rick C.

-- Get 2,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209
 
On Wednesday, September 25, 2019 at 2:59:26 PM UTC-4, bitrex wrote:
On 9/25/19 2:40 PM, George Herold wrote:
On Wednesday, September 25, 2019 at 1:45:08 PM UTC-4, bitrex wrote:
On 9/25/19 10:47 AM, Rick C wrote:
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
0000
1000
1100
1110
1111
0111
0011
0001

disalowed
0100
1010
1101
0110
1011
0101
0010
1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The only practical, glitchless methods I know of for this use are the thermometer code or the Johnson ring counter. A grey code is glitchless, but I can't see a useful way to apply it here.


Integrated 4000-series Johnson counters are said to use this logic
between every 3rd flop stage to error-correct:

https://mysite.du.edu/~etuttle/electron/circ418.gif

Why not just use a counter/ divider '4017 or '4022?
https://www.ti.com/lit/ds/symlink/cd4017b.pdf

George H.


4000 series are too slow at low voltage at the speed I need to go at.
What voltage? 74HC4017?
Click to expand...

GH
"01" on the final two outputs is either the end of a proper count, or
part of an error cycle.

For a four-flop ring that requires a negative-going reset pulse a diode
OR gate from not-Q and Q on the last two flops to bang a pulse to ground
into CLR when it hits that state seems simple enough...
Click to expand...
 
On Wednesday, September 25, 2019 at 2:45:46 PM UTC-4, Tauno Voipio wrote:
On 25.9.19 21:40, George Herold wrote:
On Wednesday, September 25, 2019 at 1:45:08 PM UTC-4, bitrex wrote:
On 9/25/19 10:47 AM, Rick C wrote:
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
0000
1000
1100
1110
1111
0111
0011
0001

disalowed
0100
1010
1101
0110
1011
0101
0010
1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The only practical, glitchless methods I know of for this use are the thermometer code or the Johnson ring counter. A grey code is glitchless, but I can't see a useful way to apply it here.


Integrated 4000-series Johnson counters are said to use this logic
between every 3rd flop stage to error-correct:

https://mysite.du.edu/~etuttle/electron/circ418.gif

Why not just use a counter/ divider '4017 or '4022?
https://www.ti.com/lit/ds/symlink/cd4017b.pdf

George H.


The ripple counter and decoder combination is a way to invite
glitch problems. The decoded states do not produce the thermometer
code (KITT front decoration) needed to create the sine waves.

I suggested at the start of this thread how to create reliable
thermometer codes counters.
Click to expand...
The divider has ten outputs, you hang the right R on the output and
sum them all into an opamp, AC couple and filter to taste. :^)

I did this several years ago, worked great.

George H.
--

-TV
Click to expand...
 
On 9/25/19 2:40 PM, George Herold wrote:
On Wednesday, September 25, 2019 at 1:45:08 PM UTC-4, bitrex wrote:
On 9/25/19 10:47 AM, Rick C wrote:
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
0000
1000
1100
1110
1111
0111
0011
0001

disalowed
0100
1010
1101
0110
1011
0101
0010
1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The only practical, glitchless methods I know of for this use are the thermometer code or the Johnson ring counter. A grey code is glitchless, but I can't see a useful way to apply it here.


Integrated 4000-series Johnson counters are said to use this logic
between every 3rd flop stage to error-correct:

https://mysite.du.edu/~etuttle/electron/circ418.gif

Why not just use a counter/ divider '4017 or '4022?
https://www.ti.com/lit/ds/symlink/cd4017b.pdf

George H.
Click to expand...

4000 series are too slow at low voltage at the speed I need to go at.

"01" on the final two outputs is either the end of a proper count, or
part of an error cycle.

For a four-flop ring that requires a negative-going reset pulse a diode
OR gate from not-Q and Q on the last two flops to bang a pulse to ground
into CLR when it hits that state seems simple enough...
 
On 25.9.19 21:40, George Herold wrote:
On Wednesday, September 25, 2019 at 1:45:08 PM UTC-4, bitrex wrote:
On 9/25/19 10:47 AM, Rick C wrote:
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf

Given that most D flops have not-Q that's all the patent is, a NOR gate
connected from two outputs to clear. for 20 years until 2005 you'd need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one, perhaps in
different IC packages even, I think actively rejecting dis-allowed walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
0000
1000
1100
1110
1111
0111
0011
0001

disalowed
0100
1010
1101
0110
1011
0101
0010
1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with the resulting race and glitching that started us down this rabbit hole.

The only practical, glitchless methods I know of for this use are the thermometer code or the Johnson ring counter. A grey code is glitchless, but I can't see a useful way to apply it here.


Integrated 4000-series Johnson counters are said to use this logic
between every 3rd flop stage to error-correct:

https://mysite.du.edu/~etuttle/electron/circ418.gif

Why not just use a counter/ divider '4017 or '4022?
https://www.ti.com/lit/ds/symlink/cd4017b.pdf

George H.
Click to expand...

The ripple counter and decoder combination is a way to invite
glitch problems. The decoded states do not produce the thermometer
code (KITT front decoration) needed to create the sine waves.

I suggested at the start of this thread how to create reliable
thermometer codes counters.

--

-TV
 
On 9/25/19 2:59 PM, bitrex wrote:
On 9/25/19 2:40 PM, George Herold wrote:
On Wednesday, September 25, 2019 at 1:45:08 PM UTC-4, bitrex wrote:
On 9/25/19 10:47 AM, Rick C wrote:
On Tuesday, September 24, 2019 at 3:31:24 AM UTC-4, Jasen Betts wrote:
On 2019-09-23, bitrex <user@example.net> wrote:
Incidentally, Bell Labs patented using a NOR gate to reject
dis-allowed
states in ring counters in 1987:

https://patentimages.storage.googleapis.com/63/46/96/e86652e4b418f1/US4646332.pdf


Given that most D flops have not-Q that's all the patent is, a NOR
gate
connected from two outputs to clear. for 20 years until 2005 you'd
need
to ask Bell Lab's permission if you wanna do that! Heh!

Anyway the point is when using discrete flops to build one,
perhaps in
different IC packages even, I think actively rejecting dis-allowed
walks
is important thing.

for a four-flop counter I think a quad-input XOR can generate a reset
for the dis-allowed states just by "inspection." If your outputs are
ever 1010 or 0101 it's gone sideways.

quad input xor? all the legal paterns have a hamming distance of one
from their neighbours, that's not going to work.

there's 8 allowed states and 8 disallowed states

allowed
   0000
   1000
   1100
   1110
   1111
   0111
   0011
   0001

disalowed
   0100
   1010
   1101
   0110
   1011
   0101
   0010
   1001

as they form a ring you only need to detect one of those or a
sub-pattern that does not occur in legal paterns such as such as 010x
for that 3-input and will do (assuming ~Q outputs are available)

or just use a CD4022 and use resistors from the outputs to make your
sine and cosine signals.

Except that gets us back to multiple outputs changing at once with
the resulting race and glitching that started us down this rabbit hole.

The only practical, glitchless methods I know of for this use are
the thermometer code or the Johnson ring counter.  A grey code is
glitchless, but I can't see a useful way to apply it here.


Integrated 4000-series Johnson counters are said to use this logic
between every 3rd flop stage to error-correct:

https://mysite.du.edu/~etuttle/electron/circ418.gif

Why not just use a counter/ divider '4017 or '4022?
https://www.ti.com/lit/ds/symlink/cd4017b.pdf

George H.


4000 series are too slow at low voltage at the speed I need to go at.

"01" on the final two outputs is either the end of a proper count, or
part of an error cycle.

For a four-flop ring that requires a negative-going reset pulse a diode
OR gate from not-Q and Q
Click to expand...

Sorry, reverse that. I think.
 
On Wednesday, September 25, 2019 at 5:25:34 PM UTC-4, bitrex wrote:
On 9/25/19 3:24 PM, George Herold wrote:

Why not just use a counter/ divider '4017 or '4022?
https://www.ti.com/lit/ds/symlink/cd4017b.pdf

George H.


4000 series are too slow at low voltage at the speed I need to go at.
What voltage? 74HC4017?

GH

1.8, idk if there are any appropriate Johnson counter in the 74LVC series.
Click to expand...

I don't think you look very hard.

https://assets.nexperia.com/documents/data-sheet/74LV164.pdf

--

Rick C.

-- Get 2,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209
 
On 9/25/19 3:24 PM, George Herold wrote:

Why not just use a counter/ divider '4017 or '4022?
https://www.ti.com/lit/ds/symlink/cd4017b.pdf

George H.


4000 series are too slow at low voltage at the speed I need to go at.
What voltage? 74HC4017?

GH
Click to expand...

1.8, idk if there are any appropriate Johnson counter in the 74LVC series.
 
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