reset strategy FPGA Igloo

[alb]

Hi Rick,

On 08/11/2013 15:47, rickman wrote:
[]

According to the FAE it is possible to configure the internal weak
pull-up resistor on the PIN configuration and profit of the same
mechanism described in the AN I was referring to
(http://www.actel.com/documents/LPF_AC380_AN.pdf), therefore
*without* the need of an additional external pull up resistor.

The app note goes into great detail about the timing of VCC and VCCI.
In this discussion I believe they are talking about the input from
the IBUF (RST_p) when they say, "The I/Os are tristated and the core
logic detects '1' on the inputs from the boundary scan register
(BSR)." It is not clear what sets the value in the BSR. It is also
not clear how this determines the value of the RST_p signal.

Between the I/O Bank and the FPGA core there's the BSR mandated by the
IEEE-1149.1 standard (JTAG) that you can control during programming. I'm
trying to look for 'default' values, but that is not essential since
when both VCC and VCCI will be above the functional voltage level the
I/O will first drive the input and 200ns later the output, resulting in
the transition '1'->'0' on RST_p which, in turns, generates a transition
'0'->'1' on RST_n, to be used internally as an active low reset.

This entire circuit seems to depend on VCC reaching "its functional
voltage level" before VCCI. Do you know that this is true for your
board?

Actually you do not need to have VCC functional *before* VCCI. I paste
here an excerpt from the app note:

(pag.2)

Before the start of power-up, all the I/Os are tristated. The I/Os
remain tristated during the power-up until the last supply (being
either VCCIBx or VCC) is powered to its functional activation voltage
level. After the last supply reaches the functional voltage level,
the outputs of the active I/O bank exits the tristate mode and drive
the logic at the input of the output buffer. Similarly, the input
buffers of the active I/O bank passes the external logic into the
FPGA fabric once the last supply reaches its functional voltage
level. The behavior of user I/Os is independent of the VCC and VCCIBx
power-up sequence

HTH,

Al

 

[rickman]

On 11/13/2013 6:43 AM, alb wrote:

Hi Rick,

On 08/11/2013 15:47, rickman wrote:
[]
According to the FAE it is possible to configure the internal weak
pull-up resistor on the PIN configuration and profit of the same
mechanism described in the AN I was referring to
(http://www.actel.com/documents/LPF_AC380_AN.pdf), therefore
*without* the need of an additional external pull up resistor.

The app note goes into great detail about the timing of VCC and VCCI.
In this discussion I believe they are talking about the input from
the IBUF (RST_p) when they say, "The I/Os are tristated and the core
logic detects '1' on the inputs from the boundary scan register
(BSR)." It is not clear what sets the value in the BSR. It is also
not clear how this determines the value of the RST_p signal.

Between the I/O Bank and the FPGA core there's the BSR mandated by the
IEEE-1149.1 standard (JTAG) that you can control during programming. I'm
trying to look for 'default' values, but that is not essential since
when both VCC and VCCI will be above the functional voltage level the
I/O will first drive the input and 200ns later the output, resulting in
the transition '1'->'0' on RST_p which, in turns, generates a transition
'0'->'1' on RST_n, to be used internally as an active low reset.

This entire circuit seems to depend on VCC reaching "its functional
voltage level" before VCCI. Do you know that this is true for your
board?

Actually you do not need to have VCC functional *before* VCCI. I paste
here an excerpt from the app note:

(pag.2)
Before the start of power-up, all the I/Os are tristated. The I/Os
remain tristated during the power-up until the last supply (being
either VCCIBx or VCC) is powered to its functional activation voltage
level. After the last supply reaches the functional voltage level,
the outputs of the active I/O bank exits the tristate mode and drive
the logic at the input of the output buffer. Similarly, the input
buffers of the active I/O bank passes the external logic into the
FPGA fabric once the last supply reaches its functional voltage
level. The behavior of user I/Os is independent of the VCC and VCCIBx
power-up sequence

I hope all this is clear to you, it is not clear to me. But if it
works, then great. There's your solution. Will you have to prove to
someone that this will work in a real system by analyzing the vendor's
documents? That might be a bit tough.

BTW, what is the fabric logic doing while all this Vcc ramping is going
on. What does it do if the logic VCC ramps up before VCCI does? I
guess if the I/Os are not enabled it doesn't matter much what it does if
it gets a reset pulse before the outputs are enabled. Can you assure that?

--

Rick

 

[alb]

Hi Rick,

On 14/11/2013 02:10, rickman wrote:

The app note goes into great detail about the timing of VCC and VCCI.
In this discussion I believe they are talking about the input from
the IBUF (RST_p) when they say, "The I/Os are tristated and the core
logic detects '1' on the inputs from the boundary scan register
(BSR)." It is not clear what sets the value in the BSR. It is also
not clear how this determines the value of the RST_p signal.

Between the I/O Bank and the FPGA core there's the BSR mandated by the
IEEE-1149.1 standard (JTAG) that you can control during programming. I'm
trying to look for 'default' values, but that is not essential since
when both VCC and VCCI will be above the functional voltage level the
I/O will first drive the input and 200ns later the output, resulting in
the transition '1'->'0' on RST_p which, in turns, generates a transition
'0'->'1' on RST_n, to be used internally as an active low reset.

This entire circuit seems to depend on VCC reaching "its functional
voltage level" before VCCI. Do you know that this is true for your
board?

Actually you do not need to have VCC functional *before* VCCI. I paste
here an excerpt from the app note:

(pag.2)
Before the start of power-up, all the I/Os are tristated. The I/Os
remain tristated during the power-up until the last supply (being
either VCCIBx or VCC) is powered to its functional activation voltage
level. After the last supply reaches the functional voltage level,
the outputs of the active I/O bank exits the tristate mode and drive
the logic at the input of the output buffer. Similarly, the input
buffers of the active I/O bank passes the external logic into the
FPGA fabric once the last supply reaches its functional voltage
level. The behavior of user I/Os is independent of the VCC and VCCIBx
power-up sequence

I hope all this is clear to you, it is not clear to me. But if it
works, then great. There's your solution.

I do not get what is not clear for you, it might be I'm missing something.

Will you have to prove to
someone that this will work in a real system by analyzing the vendor's
documents? That might be a bit tough.

Not more than proving that any other piece of the logic works. My system
is relying on the internal PLL properly working and I only have the
datasheet to consult. What else should i be considering?

BTW, what is the fabric logic doing while all this Vcc ramping is going
on. What does it do if the logic VCC ramps up before VCCI does? I
guess if the I/Os are not enabled it doesn't matter much what it does if
it gets a reset pulse before the outputs are enabled. Can you assure that?

The I/O are tristated until the *last* supply is powered. What the
internal logic does before that point is kind of useless to speculate on
since whichever state will end up with it will come back to a known one
after reset.

 

[rickman]

On 11/14/2013 11:24 AM, alb wrote:

Hi Rick,

On 14/11/2013 02:10, rickman wrote:
[]
The app note goes into great detail about the timing of VCC and VCCI.
In this discussion I believe they are talking about the input from
the IBUF (RST_p) when they say, "The I/Os are tristated and the core
logic detects '1' on the inputs from the boundary scan register
(BSR)." It is not clear what sets the value in the BSR. It is also
not clear how this determines the value of the RST_p signal.

Between the I/O Bank and the FPGA core there's the BSR mandated by the
IEEE-1149.1 standard (JTAG) that you can control during programming. I'm
trying to look for 'default' values, but that is not essential since
when both VCC and VCCI will be above the functional voltage level the
I/O will first drive the input and 200ns later the output, resulting in
the transition '1'->'0' on RST_p which, in turns, generates a transition
'0'->'1' on RST_n, to be used internally as an active low reset.

This entire circuit seems to depend on VCC reaching "its functional
voltage level" before VCCI. Do you know that this is true for your
board?

Actually you do not need to have VCC functional *before* VCCI. I paste
here an excerpt from the app note:

(pag.2)
Before the start of power-up, all the I/Os are tristated. The I/Os
remain tristated during the power-up until the last supply (being
either VCCIBx or VCC) is powered to its functional activation voltage
level. After the last supply reaches the functional voltage level,
the outputs of the active I/O bank exits the tristate mode and drive
the logic at the input of the output buffer. Similarly, the input
buffers of the active I/O bank passes the external logic into the
FPGA fabric once the last supply reaches its functional voltage
level. The behavior of user I/Os is independent of the VCC and VCCIBx
power-up sequence

I hope all this is clear to you, it is not clear to me. But if it
works, then great. There's your solution.

I do not get what is not clear for you, it might be I'm missing something.

There is language in the documents you have provided that is not clear.
They talk about the boundary scan logic but don't explain how this
impacts the start up operation.

Will you have to prove to
someone that this will work in a real system by analyzing the vendor's
documents? That might be a bit tough.

Not more than proving that any other piece of the logic works. My system
is relying on the internal PLL properly working and I only have the
datasheet to consult. What else should i be considering?

But you *aren't* relying on the data sheet. You are relying on an app
note that seems to have gaps from what I have seen. I just can't fully
grasp how the chip is expected to operate. They have boundary scan
logic which has to be reset on power up. Where does that reset come
from? Does the boundary scan logic impact this reset strategy at all?
Can you show this from the documentation?

BTW, what is the fabric logic doing while all this Vcc ramping is going
on. What does it do if the logic VCC ramps up before VCCI does? I
guess if the I/Os are not enabled it doesn't matter much what it does if
it gets a reset pulse before the outputs are enabled. Can you assure that?

The I/O are tristated until the *last* supply is powered. What the
internal logic does before that point is kind of useless to speculate on
since whichever state will end up with it will come back to a known one
after reset.

The IOs are tristated, but what is going on with the inputs? This is
all being explained piecemeal so I can't see the full picture to know
that all of the timing works. Also realize that I read your post and
try to remember what you have written. Then I don't think about this
for days until the next post. So I don't remember all the details. If
you have explained something a week ago I have long since forgotten it.

If you are happy, then it doesn't matter if I understand it. But from
what you have said, there will be some sort of review of your approach.
You need to be able to justify all this adequately for the review.

--

Rick

 

[alb]

Hi Rick,

On 15/11/2013 08:20, rickman wrote:
[]

(pag.2)
Before the start of power-up, all the I/Os are tristated. The I/Os
remain tristated during the power-up until the last supply (being
either VCCIBx or VCC) is powered to its functional activation voltage
level. After the last supply reaches the functional voltage level,
the outputs of the active I/O bank exits the tristate mode and drive
the logic at the input of the output buffer. Similarly, the input
buffers of the active I/O bank passes the external logic into the
FPGA fabric once the last supply reaches its functional voltage
level. The behavior of user I/Os is independent of the VCC and VCCIBx
power-up sequence

I hope all this is clear to you, it is not clear to me. But if it
works, then great. There's your solution.

I do not get what is not clear for you, it might be I'm missing
something.

There is language in the documents you have provided that is not clear.
They talk about the boundary scan logic but don't explain how this
impacts the start up operation.

Well, it is possible that i misunderstood that part, but reading the
app. note again it looks to me that when the I/O is *not* enabled (i.e.
prior to both VCC and VCCIBx operational) the fabric logic is driven by
the BSR register.

Since prior to both VCC and VCCIBx operational the I/O is tristated, I
do not care much about what is going on internally since it is not going
to affect the I/O.

OTOH when both VCC and VCCIBx are operational there's a sequence of
'activation' of the input first and the output secondly which provides
the '0'->'1' condition for an active low reset labelled in the document
as RST_n.

Will you have to prove to
someone that this will work in a real system by analyzing the vendor's
documents? That might be a bit tough.

Not more than proving that any other piece of the logic works. My system
is relying on the internal PLL properly working and I only have the
datasheet to consult. What else should i be considering?

But you *aren't* relying on the data sheet. You are relying on an app
note that seems to have gaps from what I have seen. I just can't fully
grasp how the chip is expected to operate. They have boundary scan
logic which has to be reset on power up. Where does that reset come
from? Does the boundary scan logic impact this reset strategy at all?

The BSR is normally 'reset' through the JTAG port (either synchronously
or asynchronously), but does not really matter because when the JTAG is
not active the chip drives output from its internal fabric and samples
input transparently.

> Can you show this from the documentation?

Nope, I'm trying to look for the JTAG implementation description of this
device, but I'm having hard time to find it.

[]

The I/O are tristated until the *last* supply is powered. What the
internal logic does before that point is kind of useless to speculate on
since whichever state will end up with it will come back to a known one
after reset.

The IOs are tristated, but what is going on with the inputs? This is
all being explained piecemeal so I can't see the full picture to know
that all of the timing works. Also realize that I read your post and
try to remember what you have written. Then I don't think about this
for days until the next post. So I don't remember all the details. If
you have explained something a week ago I have long since forgotten it.

I completely understand.

If you are happy, then it doesn't matter if I understand it. But from
what you have said, there will be some sort of review of your approach.
You need to be able to justify all this adequately for the review.

Yep!

 

[rickman]

On 11/18/2013 11:13 AM, alb wrote:

Hi Rick,

On 15/11/2013 08:20, rickman wrote:
The IOs are tristated, but what is going on with the inputs? This is
all being explained piecemeal so I can't see the full picture to know
that all of the timing works. Also realize that I read your post and
try to remember what you have written. Then I don't think about this
for days until the next post. So I don't remember all the details. If
you have explained something a week ago I have long since forgotten it.

I completely understand.

I think in terms of pictures, so I probably wouldn't fully understand
all of this until I saw a timing diagram. Nothing fancy, just something
that shows all the events in a timeline along with the various signals
in the reset chain. I suspect something like this would be good
material for your review. I believe the events are like this...

Vcc _____------------
VccIO ________---------

--or--

Vcc ________---------
VccIO _____------------

-- results --

BSR drives internal logic, High = drives, Lo = not driving
---------________

Inputs enabled
_________--------
Outputs enabled
____________-----
Input to reset logic
xxxxxxxxx---_____

The reset is your reset circuit for the rest of the chip.

Now that I see it in diagram form, I think you have it covered.

--

Rick