Request for feedback: proposed new Perl modules to aid VHDL

  • Thread starter Michael Attenborough
  • Start date
Mike Treseler <mike_treseler@comcast.net> writes:

Configurations are neater once finished.
However, it can be mind-numbing getting them that way.
The real downside for me is maintaining the components and
entities separately and verifying that the complete
set of tools can understand them.
But Emacs' VHDL-mode can create you a single VHD file with all your
components in it at the click of a mouse :)

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt
 
Martin Thompson wrote:

But Emacs' VHDL-mode can create you a single VHD file with all your
components in it at the click of a mouse :)
Yes it can. I do use the vhdl-compose commands for creating
structural top-entities but I keep vhdl-use-direct-instantiation
turned on. If you turn if off, vhdl-mode can make component
declarations for you and collect them in a package.
If you like configurations this is probably the easiest
way to do it. However vhdl-use-direct-instantiation is a
global, not a project setting.

To do a gate sim in vhdl-mode, I define a separate
project directory containing only the synthesis
netlist (.vho) work directory and Makefile.
The testbench and vendor libraries are compiled
in by reference from other directories.
This works fine and keeps my design projects
clean and simple.

-- Mike Treseler
 

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