receiving data

[blackpadme]

Hi,

I'm coding a data receiver which manage bits sent with period Tb. I
need to do some operations with the actual input and the previous, and
then, output the result.

When i get the data from the channel, doing:

get_data : process(clk, en)
variable ...
begin
if en = '1' and rising_edge(clk) then
temp_input := input;
do things with input and the last value..

output <= result;
end process;

I get a lag of Tb in the output. Is normal have this lag connecting
sequential devices to other sequential devices receiving the data with
a clock ?

Thanks.

 

[Mike Treseler]

blackpadme wrote:

...
output <= result;
end process;

I get a lag of Tb in the output. Is normal have this lag connecting
sequential devices to other sequential devices receiving the data with
a clock ?

Yes. In your example,
"result" is on the D side of the register, and
"output" is on the Q side.

-- Mike Treseler