A
Alan Fitch
Guest
Andy wrote:
a continuum of pulse rejection limits. To quote the VHDL standard
"-- The following three assignments are equivalent to each other:
Output_pin <= Input_pin after 10 ns;
Output_pin <= inertial Input_pin after 10 ns;
Output_pin <= reject 10 ns inertial Input_pin after 10 ns;"
So inertial delay is like having a pulse rejection limit as long as the
specified delay, whereas transport delay is like having a pulse
rejection limit of 0.
regards
Alan
--
Alan Fitch
Doulos
http://www.doulos.com
One way to think of inertial delay and transport delay is as the ends ofIn my way of thinking, Inertial and Transport mechanisms are opposite
of each other. If (and I don't think it does) the inertial delay
mechanism is causing some behavior (discarding all but the last of all
non-delayed outputs in the delta cycle following the process cycle),
then transport delay ought to avoid that behavior (allow the multiple
outputs to appear), which we both agree will not happen.
a continuum of pulse rejection limits. To quote the VHDL standard
"-- The following three assignments are equivalent to each other:
Output_pin <= Input_pin after 10 ns;
Output_pin <= inertial Input_pin after 10 ns;
Output_pin <= reject 10 ns inertial Input_pin after 10 ns;"
So inertial delay is like having a pulse rejection limit as long as the
specified delay, whereas transport delay is like having a pulse
rejection limit of 0.
regards
Alan
--
Alan Fitch
Doulos
http://www.doulos.com