Reading 16 bit words from a file

F

Fredxx

Guest
I'm using the following lines which can read binary data from a file.

signal data_char : STD_LOGIC_VECTOR(15 downto 0);

type character_file is file of character;
file myfile: character_file;
variable character_variable : character;

file_open ( myfile, "file_name", read_mode);
read(myfile, character_variable);
data_word <= CONV_STD_LOGIC_VECTOR(character'pos(character_variable), 16);


But as is expected the 'character' is only 8 bits and only populates the
lower 8 bits of data_word.

Is VHDL able to read in 16 bit data, or should I give up now?
 
Fredxx wrote:
I'm using the following lines which can read binary data from a file.

signal data_char : STD_LOGIC_VECTOR(15 downto 0);

type character_file is file of character;
file myfile: character_file;
variable character_variable : character;

file_open ( myfile, "file_name", read_mode);
read(myfile, character_variable);
data_word <= CONV_STD_LOGIC_VECTOR(character'pos(character_variable), 16);


But as is expected the 'character' is only 8 bits and only populates the
lower 8 bits of data_word.

Is VHDL able to read in 16 bit data, or should I give up now?
Click to expand...
Yes, but not not like that.
Consider using vhdl constants as demonstrated in the previous thread.

-- Mike Treseler
 
"Mike Treseler" <mtreseler@gmail.com> wrote in message
news:7dp78mF2bi4egU1@mid.individual.net...
Fredxx wrote:
I'm using the following lines which can read binary data from a file.

signal data_char : STD_LOGIC_VECTOR(15 downto 0);

type character_file is file of character;
file myfile: character_file;
variable character_variable : character;

file_open ( myfile, "file_name", read_mode);
read(myfile, character_variable);
data_word <= CONV_STD_LOGIC_VECTOR(character'pos(character_variable),
16);


But as is expected the 'character' is only 8 bits and only populates the
lower 8 bits of data_word.

Is VHDL able to read in 16 bit data, or should I give up now?

Yes, but not not like that.
Consider using vhdl constants as demonstrated in the previous thread.

-- Mike Treseler
Click to expand...
I did note your dislike of textio, however this is data from another
program, so it wouldn't be straightforward to place in a constant array.

Unless of course you know of any utilities which convert a binary file
simply into a constant array VHDL file?
 
Fredxx wrote:

I did note your dislike of textio, however this is data from another
program, so it wouldn't be straightforward to place in a constant array.

Unless of course you know of any utilities which convert a binary file
simply into a constant array VHDL file?
Click to expand...
If it were a one-time conversion, I would use an emacs macro.
Otherwise, a python script.

Here a binary file example without textio:
http://mysite.verizon.net/miketreseler/char_file.vhd

Good luck.

-- Mike Treseler
 
"Fredxx" <fredxx@spam.com> writes:

But as is expected the 'character' is only 8 bits and only populates the
lower 8 bits of data_word.

Is VHDL able to read in 16 bit data, or should I give up now?
Click to expand...
You can read a byte at the time and stuff them into a 16-bit word. Not
very elegant and not very portable, but...

variable byte : character;
variable bin16 : natural;

read(img_file, byte);
bin16 := character'pos(byte);
read(img_file, byte);
bin16 := bin16 + (256 * character'pos(byte)); -- little endian
return std_logic_vector(to_unsigned(bin16, 16));

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
On Aug 3, 10:38 pm, "Fredxx" <fre...@spam.com> wrote:
I'm using the following lines which can read binary data from a file.

signal data_char : STD_LOGIC_VECTOR(15 downto 0);

type character_file is file of character;
file myfile: character_file;
variable character_variable : character;

file_open ( myfile, "file_name", read_mode);
read(myfile, character_variable);
data_word <= CONV_STD_LOGIC_VECTOR(character'pos(character_variable), 16);

But as is expected the 'character' is only 8 bits and only populates the
lower 8 bits of data_word.

Is VHDL able to read in 16 bit data, or should I give up now?
Click to expand...
If you know the length of "data_word" just create a for loop to read
each character into the different bytes of it.

FILE_OPEN(myfile, "file_name", read_mode)

for i in 0 to N_BYTES-1 loop
read(myfile, c_buf);
data_word((i+1)*8 -1 downto i*8) <= std_logic_vector(
to_unsigned(
character'pos(c_buf), 8
)
);
end loop;
 
"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message
news:87k51k0zai.fsf@pangea.home.gustad.com...
"Fredxx" <fredxx@spam.com> writes:

But as is expected the 'character' is only 8 bits and only populates the
lower 8 bits of data_word.

Is VHDL able to read in 16 bit data, or should I give up now?

You can read a byte at the time and stuff them into a 16-bit word. Not
very elegant and not very portable, but...

variable byte : character;
variable bin16 : natural;

read(img_file, byte);
bin16 := character'pos(byte);
read(img_file, byte);
bin16 := bin16 + (256 * character'pos(byte)); -- little endian
return std_logic_vector(to_unsigned(bin16, 16));
Click to expand...
That's what I've ended up doing, in fact using the -ve going clock to take
one byte and +ve clock the other byte.

I just wondered if there was a more elegant method :)
 
"Mike Treseler" <mtreseler@gmail.com> wrote in message
news:7dpde1F2cnurkU1@mid.individual.net...
Fredxx wrote:

I did note your dislike of textio, however this is data from another
program, so it wouldn't be straightforward to place in a constant array.

Unless of course you know of any utilities which convert a binary file
simply into a constant array VHDL file?

If it were a one-time conversion, I would use an emacs macro.
Otherwise, a python script.

Here a binary file example without textio:
http://mysite.verizon.net/miketreseler/char_file.vhd

Good luck.
Click to expand...
Many thanks.

In essence I'm taking an intermediate output from a C++ program and
comparing outputs from a VHDL simulation with the output from the same C++
program. When it comes to numerical algorithms I find it easier to prove
and debug a program in C or similar and then transcribe into VHDL for a
hardware implementation.
 
On Tue, 4 Aug 2009 11:28:48 +0100, "Fredxx" <fredxx@spam.com> wrote:


Many thanks.

In essence I'm taking an intermediate output from a C++ program and
comparing outputs from a VHDL simulation with the output from the same C++
program. When it comes to numerical algorithms I find it easier to prove
and debug a program in C or similar and then transcribe into VHDL for a
hardware implementation.
Click to expand...
If it's your C program, then creating the VHDL constant array (most simply as a
separate package) is a small matter of printf's. Job done.

If you need binary file I/O (as opposed to textio), e.g. to read .jpgs, Mike's
example is a good starting point, but be aware that binary I/O in VHDL works but
not portably. For example, Xilinx ISE 10.1 simulator expects to see an
undocumented* 9-byte header before the data, and is endian-swapped compared to
Modelsim.

*Xilinx support have declined to release the format on request. Stripping the
header from an ISIM output file and cat'ing it onto a 3rd party binary works,
but it's ugly.

- Brian
 
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