Read and Write process verification

Hi All,

Presently i am working on a verification project and writing
Testcase's for a funtional element requirements.

I have a requirement: Bit 0 of the rcom_ctl_sts register returns a 1
within 1 us when a one valid message has been received on the RCOM
receiver and written to buffer 0.

So for this requirement i am writing steps to verify a valid rcom
message (with Manchester encoding) received to buffer 0.

The rcom message where its format is : Start Bits - Header word - Data
word- Check word - Parity

Steps:
-------
1). After transmition a single word message
2). I am reading the every rcom message word from the register
READ (0x01080) // Read process, and this register gives header
READ (0x01081) // This register address gives data word

so my question is Can we READ these values continously without any
waiting or
We should be wait for some time and then read next value.

Say : WAIT FOR 50 ns
READ (0x01080)
WAIT FOR 50 ns
READ (0x01081)
Is this correct way or without waiting Reading the values is correct
way?

Where all the values will displays on dsp_d(31:0) output signal.

Please anyone suggest me which one has to follow...

Sreeni.J

 

[Mike Treseler]

shrinivas.jyothi@gmail.com wrote:

We should wait for some time and then read next value.

Yes, unless your read procedure has enough delay.

Say : WAIT FOR 50 ns
READ (0x01080)
WAIT FOR 50 ns
READ (0x01081)

That would be ok with a few of these ';'

I would prefer to say
handshake(rd_ack_s,clk_en_s);
using procedures something like this:

procedure tic (arg : natural := 1) is
begin
for i in 1 to arg loop
wait until rising_edge(clk_s);
end loop;
end procedure tic;

procedure handshake(
signal waiting_on : in std_ulogic;
signal enable : inout std_ulogic;
happy : in string := "handshake: Saw ack.";
sad : in string := "handshake: Gave up waiting.";
goal : in std_ulogic := '1';
bail : in natural := 10)
is
variable delay_v : natural := 0;
begin
while waiting_on /= goal loop
-- report("handshake: waiting ");
delay_v := delay_v + 1;
if delay_v = bail then
report sad;
tic(10)
enable <= '0'; -- stop sim clock
tic;
end if;
tic; -- wait one sim clock period
end loop;
--report(happy);
end procedure handshake;

Where all the values will displays on dsp_d(31:0) output signal.

for modelsim use: add wave -r /*
before running the sim.

-- Mike Treseler