J
Jonathan Bromley
Guest
hi comp.lang.vhdl,
A few moments ago I posted a response about random time
delays, and it got me thinking: in VHDL we have
ieee.math_real.uniform() to give flat (uniform) random
distributions, but Verilog also has a bunch of other
distributions available: $dist_gaussian, $dist_poisson
and a few more. Gaussian and Poisson are both *very*
useful for testbench applications - for example, the
random timing jitter I posted about should probably
have a gaussian distribution; when modelling the
number of wait states introduced on bus read cycles,
Poisson distribution usually works well.
Has anyone done these for VHDL and made them public?
Or are they in one of the standard libraries, and
I just failed to spot them all these years? There
are C reference algorithms in the Verilog LRM, so it
should not be too difficult to reproduce them in VHDL.
thanks
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
A few moments ago I posted a response about random time
delays, and it got me thinking: in VHDL we have
ieee.math_real.uniform() to give flat (uniform) random
distributions, but Verilog also has a bunch of other
distributions available: $dist_gaussian, $dist_poisson
and a few more. Gaussian and Poisson are both *very*
useful for testbench applications - for example, the
random timing jitter I posted about should probably
have a gaussian distribution; when modelling the
number of wait states introduced on bus read cycles,
Poisson distribution usually works well.
Has anyone done these for VHDL and made them public?
Or are they in one of the standard libraries, and
I just failed to spot them all these years? There
are C reference algorithms in the Verilog LRM, so it
should not be too difficult to reproduce them in VHDL.
thanks
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.