RAM in Altera EABs and Xilinx Block Rams

[Peter Alfke]

Thanks for the (late) praise. I was really proud of my drawing.
But it gets more complicated in BRAMs, what with the write and the read
pulse dancing around each other. Still, food for thought...
Peter Alfke

I don't recall if there is also
an optional output register, if so, that should be added to the
illustration as well. I seem to recall that the operation of the CLB
RAM in the 4000E series was illustrated very well in this regards. It
showed all the possible modes via registers, muxes and the write pulse
generator. Something like that would be useful if added to Xapp 463.

 

[Ray Andraka]

Rickman,

Not sure where you got this idea. Xilinx reads take ONE clock cycle from
address to data out. In the case of pre-VirtexII, a write cycle copied the
write data to the read outputs as well. In the newer chips you have the choice
of what data comes out the read port during a write cycle.

rickman wrote:

Peter Alfke wrote:

Xilinx (Virtex2 or Spartan3) BlockRAM reading while writing:
Any write operation also performs a read, and outputs it on the Do output.
The user can choose: write before read (= output the data that is being
witten), or read before write (=output the previous content that is now
being overwritten) or "no change"( keep the old data on the Do lines.

But it still has a two cycle delay from writing to read data out,
right? So if I want the data that was just written on the next clock
cycle (like in a stack) I need to use an external register and use
separate read and write addresses. Correct?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
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--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[rickman]

Ray Andraka wrote:

Rickman,

Not sure where you got this idea. Xilinx reads take ONE clock cycle from
address to data out. In the case of pre-VirtexII, a write cycle copied the
write data to the read outputs as well. In the newer chips you have the choice
of what data comes out the read port during a write cycle.

rickman wrote:

Peter Alfke wrote:

Xilinx (Virtex2 or Spartan3) BlockRAM reading while writing:
Any write operation also performs a read, and outputs it on the Do output.
The user can choose: write before read (= output the data that is being
witten), or read before write (=output the previous content that is now
being overwritten) or "no change"( keep the old data on the Do lines.

But it still has a two cycle delay from writing to read data out,
right? So if I want the data that was just written on the next clock
cycle (like in a stack) I need to use an external register and use
separate read and write addresses. Correct?

You are responding to old messages. This has already been corrected by
Peter and others. Thanks anyway.

Just FYI, I got confused between an edge clocked register and the data
hold latch they have on the output. I am a visual guy and the app note
is mainly words which can get me confused sometimes.

-

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX