Rail Splitting Chips...

[Phil Hobbs]

On 2023-03-10 10:35, John Larkin wrote:

On Fri, 10 Mar 2023 01:59:38 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2023-03-10 01:42, John Larkin wrote:
On Fri, 10 Mar 2023 01:34:00 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2023-03-09 20:53, whit3rd wrote:
On Thursday, March 9, 2023 at 12:56:22?PM UTC-8, Phil Hobbs wrote:
On 2023-03-09 15:50, boB wrote:
On Thu, 9 Mar 2023 12:18:25 -0800 (PST), Ricky
gnuarm.del...@gmail.com> wrote:

I read some of the discussion on \"rail splitting\" ...
The obvious solution would be to set a reference point using resistors, and an op amp to provide the drive.

You would think there would be one of these but I still take 2 equal
value resistors and feed into a unity gain follower op-amp...

TI sells a dedicated rail splitter chip, the TLE2426. It costs more
than a TCA0372 and doesn\'t have nearly the oomph.

It\'s easier to design with lots of power rails, like the old NIM +/- 24V, +/- 12V, +6, GND, and Vref
all from the standard power supplies. Scaling to fast low-V logic was just a point-of-load regulator
away, but nowadays... everyone wants a tiny box with a wallwart power solution.

The only solutions NOT discused here, are multioutput DC/DC converters (you can get REAL
ground, not just synthetic) and tapped battery stacks. Some of HP\'s old 200 series oscillators
used strings of NiCd batteries, and only trickle charged from AC.

Assuming your own power supply onboard, what\'s the ideal wallwart to start with?
Maybe a Cuk AC generator at 10V, 40 kHz or so, three-wire so the GND doesn\'t carry
power current? You can rectify or double/triple to get almost anything with not much
extra hardware. Or maybe -48VDC like POE, to keep wires slender and delivered
power quiet?


We use +24V medical-grade wall warts (SL Power ME10A2403B01) that come
with a set of international adapters.

We have standardized on a 24 volt Phihong wart for most things. And a
24 volt laptop style supply for higher power.


We\'ve used the multiple-output things occasionally, but they all seem to
have these gruesome large-diameter, not-very-flexible cables with DIN
connectors. \'Clunky\' doesn\'t cover it.

Right. Make what you need from 24. That\'s easy nowadays.

It\'s less easy when doing wideband ultrasensitive measurements, but yeah.

Cheers

Phil Hobbs

Our critical measurement is jitter, and a typical target is a few ps
RMS. Switchers can play hell with that, especially ones that make,
say, 400 MHz bursts. It\'s easier to prevent those from happening on a
board, as compared to trying to filter them afterwards.

Yup. Good luck with the filtering. One of our failures (which are
fairly rare) was a 35-mm square board with three 2.15 MHz switchers on
it. Two of them were fine: one made an intermediate +13V from +24, and
the other made +5.

The -15V was made by an inverting buck, running off the +13 rail.
(Running 41V input to ground is a bit of a stretch for your normal fast
buck regulator.)

The moment that one got turned on, the whole board became an absolute
mess of high harmonics of 2.15 MHz, up to about 180 MHz. Different
places showed different peak frequencies, apparently on account of
different board resonances.

The +13 rail was well-behaved while all this was happening, so it wasn\'t
a collective oscillation--the negative input resistance of the inverting
regulator wasn\'t a problem.

Another jitter contributor is the modulation of logic device prop
delay by supply voltage ripple, which happens at any frequency but can
be filtered. FPGAs are horribly sensitive, prop delay vs Vcore.

We designed one delay generator that had the fast trigger path go
through an Artix7 FPGA. Big mistake. Delay changed 1 ps for a 70 uV
core supply change. I tore up the fast path and made it all discrete
logic and cut jitter and insertion delay both.

FPGAs are getting faster inside and slower pin-to-pin, which seems
strange to me. So we keep designing with discrete transistors and
diodes and gates and flops, kind of like you use discretes for the
critical bits. A diode OR gate works pretty well.

There are some logic parts with femtosecond jitter, but they are too
expensive for most uses.

(Replied with a new thread, \"Fast edges from cheap logic\".)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[bitrex]

On 3/9/2023 7:32 PM, Ricky wrote:

On Thursday, March 9, 2023 at 6:18:06 PM UTC-5, Lasse Langwadt Christensen wrote:
fredag den 10. marts 2023 kl. 00.12.39 UTC+1 skrev Ricky:
On Thursday, March 9, 2023 at 3:51:02 PM UTC-5, boB wrote:
On Thu, 9 Mar 2023 12:18:25 -0800 (PST), Ricky
gnuarm.del...@gmail.com> wrote:

I read some of the discussion on \"rail splitting\" and it occurred to me that there should be a market for these devices. I am working on a design that will run op amps from a single rail and I need a 6V level, that can both source and sink current. The board is really tight. Presently it is using zeners to set a level (one for each channel to reduce crosstalk), but I was looking at using an LDO, with a resistor to sink current.

But the new design is going to have some higher current requirements, and this would be a consistent load using the resistor. The obvious solution would be to set a reference point using resistors, and an op amp to provide the drive. The reference point doesn\'t need to be highly accurate or stable. A cap would reduce noise.

I\'m wondering if there are chips available that already do this providing say, 30 mA of drive/sink?
You would think there would be one of these but I still take 2 equal
value resistors and feed into a unity gain follower op-amp to supply
half-Vcc. Usually one half of a dual op-amp.

This would be a good use for a SOT-23 package....

But since it is just for bias, could use a SOT-23 NPN follower biased
up Vcc/2 + 0.65V or so.
The NPN follower would require the same resistor I would use with an LDO. So that\'s not much better, drawing the current all the time. In fact, when the load is pulling up, both the resistor and the LDO draw current!

npn+pnp follower, https://imgur.com/NhlLGGc

Does your drawing need a couple of diodes? Otherwise the output would have a dead band 1.something volts wide, no?

The small-signal AC impedance looking into the virtual ground is always
fairly low, at most whatever the small-signal AC impedance of the two
caps in parallel is.

The transistors just keep the DC operating point from getting too out of
whack. So there\'s no \"dead band\" per se, both the small and large signal
impedance looking in from the VG terminal always going to be something
relatively low, assuming that the currents being sourced and sunk are <<
than what the transistors and associated base resistors are appropriate
to provide when they turn on.

You can surely do a discrete class AB VG where the impedance looking in
will be more consistent at the cost of some idle current.

 

[Ricky]

On Saturday, March 11, 2023 at 12:10:21 PM UTC-5, bitrex wrote:

On 3/9/2023 7:32 PM, Ricky wrote:
On Thursday, March 9, 2023 at 6:18:06 PM UTC-5, Lasse Langwadt Christensen wrote:
fredag den 10. marts 2023 kl. 00.12.39 UTC+1 skrev Ricky:
On Thursday, March 9, 2023 at 3:51:02 PM UTC-5, boB wrote:
On Thu, 9 Mar 2023 12:18:25 -0800 (PST), Ricky
gnuarm.del...@gmail.com> wrote:

I read some of the discussion on \"rail splitting\" and it occurred to me that there should be a market for these devices. I am working on a design that will run op amps from a single rail and I need a 6V level, that can both source and sink current. The board is really tight. Presently it is using zeners to set a level (one for each channel to reduce crosstalk), but I was looking at using an LDO, with a resistor to sink current.

But the new design is going to have some higher current requirements, and this would be a consistent load using the resistor. The obvious solution would be to set a reference point using resistors, and an op amp to provide the drive. The reference point doesn\'t need to be highly accurate or stable. A cap would reduce noise.

I\'m wondering if there are chips available that already do this providing say, 30 mA of drive/sink?
You would think there would be one of these but I still take 2 equal
value resistors and feed into a unity gain follower op-amp to supply
half-Vcc. Usually one half of a dual op-amp.

This would be a good use for a SOT-23 package....

But since it is just for bias, could use a SOT-23 NPN follower biased
up Vcc/2 + 0.65V or so.
The NPN follower would require the same resistor I would use with an LDO. So that\'s not much better, drawing the current all the time. In fact, when the load is pulling up, both the resistor and the LDO draw current!

npn+pnp follower, https://imgur.com/NhlLGGc

Does your drawing need a couple of diodes? Otherwise the output would have a dead band 1.something volts wide, no?

The small-signal AC impedance looking into the virtual ground is always
fairly low, at most whatever the small-signal AC impedance of the two
caps in parallel is.

The transistors just keep the DC operating point from getting too out of
whack. So there\'s no \"dead band\" per se, both the small and large signal
impedance looking in from the VG terminal always going to be something
relatively low, assuming that the currents being sourced and sunk are
than what the transistors and associated base resistors are appropriate
to provide when they turn on.

You can surely do a discrete class AB VG where the impedance looking in
will be more consistent at the cost of some idle current.

Why is there no deadband? The transistors BE junction barely turn on until there is already movement in the set point. This movement is exactly what needs to be minimized.

I ran a simulation, and it give the exact results I expected. I added the diodes, and that works better, but still allows some 200 mVpp in the output and uses more parts that I\'d like. A voltage regulator with resistors to provide pull down current, is pretty good, but I don\'t like the 20 mA idle draw which is added to the 17 mA load current. Using an op amp is the best performing circuit and the smallest, and likely the cheapest, with 150 uA output ripple and 2 mA idle draw.

Here\'s the LTspice .asc file

Version 4
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TEXT 624 0 Left 2 !.tran 300m
TEXT 208 976 Left 2 ;Good Regulatiion\\nConstant 20 mA
TEXT 472 416 Left 2 ;Very Poor Regulation\\n1.45Vpp
TEXT 1432 480 Left 2 ;Adequate Regulation\\n200 mVpp
TEXT 1512 976 Left 2 ;Great Regulation\\n150 uVpp, 2 mA idle current


--

Rick C.

--- Get 1,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209

 

[whit3rd]

On Saturday, March 11, 2023 at 12:25:59 PM UTC-8, Ricky wrote:

On Saturday, March 11, 2023 at 12:10:21 PM UTC-5, bitrex wrote:
On 3/9/2023 7:32 PM, Ricky wrote:
On Thursday, March 9, 2023 at 6:18:06 PM UTC-5, Lasse Langwadt Christensen wrote:

npn+pnp follower, https://imgur.com/NhlLGGc

Does your drawing need a couple of diodes? Otherwise the output would have a dead band 1.something volts wide, no?

The small-signal AC impedance looking into the virtual ground is always
fairly low, at most whatever the small-signal AC impedance of the two
caps in parallel is.

The transistors just keep the DC operating point from getting too out of
whack. So there\'s no \"dead band\" per se, both the small and large signal
impedance looking in from the VG terminal always going to be something
relatively low...

Why is there no deadband? The transistors BE junction barely turn on until there is already movement in the set point. This movement is exactly what needs to be minimized.

If one is using one rail as a voltage reference, that\'s significant. If, however, one is just
using the rails for power, and all signals are ground-referenced, then it just works.
Common-mode tolerance is built into op amp designs, and at high frequency the
capacitors handle it, while at low frequency the high differential gain
dominates the tiny common-mode effect.

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

 

[Ricky]

On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:

On Saturday, March 11, 2023 at 12:25:59 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 12:10:21 PM UTC-5, bitrex wrote:
On 3/9/2023 7:32 PM, Ricky wrote:
On Thursday, March 9, 2023 at 6:18:06 PM UTC-5, Lasse Langwadt Christensen wrote:

npn+pnp follower, https://imgur.com/NhlLGGc

Does your drawing need a couple of diodes? Otherwise the output would have a dead band 1.something volts wide, no?

The small-signal AC impedance looking into the virtual ground is always
fairly low, at most whatever the small-signal AC impedance of the two
caps in parallel is.

The transistors just keep the DC operating point from getting too out of
whack. So there\'s no \"dead band\" per se, both the small and large signal
impedance looking in from the VG terminal always going to be something
relatively low...
Why is there no deadband? The transistors BE junction barely turn on until there is already movement in the set point. This movement is exactly what needs to be minimized.
If one is using one rail as a voltage reference, that\'s significant. If, however, one is just
using the rails for power, and all signals are ground-referenced, then it just works.
Common-mode tolerance is built into op amp designs, and at high frequency the
capacitors handle it, while at low frequency the high differential gain
dominates the tiny common-mode effect.

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209

 

[bitrex]

On 3/11/2023 4:41 PM, Ricky wrote:

On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:
On Saturday, March 11, 2023 at 12:25:59 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 12:10:21 PM UTC-5, bitrex wrote:
On 3/9/2023 7:32 PM, Ricky wrote:
On Thursday, March 9, 2023 at 6:18:06 PM UTC-5, Lasse Langwadt Christensen wrote:

npn+pnp follower, https://imgur.com/NhlLGGc

Does your drawing need a couple of diodes? Otherwise the output would have a dead band 1.something volts wide, no?

The small-signal AC impedance looking into the virtual ground is always
fairly low, at most whatever the small-signal AC impedance of the two
caps in parallel is.

The transistors just keep the DC operating point from getting too out of
whack. So there\'s no \"dead band\" per se, both the small and large signal
impedance looking in from the VG terminal always going to be something
relatively low...
Why is there no deadband? The transistors BE junction barely turn on until there is already movement in the set point. This movement is exactly what needs to be minimized.
If one is using one rail as a voltage reference, that\'s significant. If, however, one is just
using the rails for power, and all signals are ground-referenced, then it just works.
Common-mode tolerance is built into op amp designs, and at high frequency the
capacitors handle it, while at low frequency the high differential gain
dominates the tiny common-mode effect.

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.

For the price of two transistors, two caps, and two resistor it can sink
or source appreciable DC current from either rail while drawing zero
quiescent current. Which two caps and two resistors can\'t do without the
bias string drawing the same DC quiescent current as the max you wanna
source or sink.

Your LDO \"virtual ground\" can\'t sink current either, it\'s only \"sinking\"
cuz your sense divider is pulling 20 mA all day.

 

[bitrex]

On 3/12/2023 1:54 AM, bitrex wrote:

On 3/11/2023 4:41 PM, Ricky wrote:
On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:
On Saturday, March 11, 2023 at 12:25:59 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 12:10:21 PM UTC-5, bitrex wrote:
On 3/9/2023 7:32 PM, Ricky wrote:
On Thursday, March 9, 2023 at 6:18:06 PM UTC-5, Lasse Langwadt
Christensen wrote:

npn+pnp follower, https://imgur.com/NhlLGGc

Does your drawing need a couple of diodes? Otherwise the output
would have a dead band 1.something volts wide, no?

The small-signal AC impedance looking into the virtual ground is
always
fairly low, at most whatever the small-signal AC impedance of the two
caps in parallel is.

The transistors just keep the DC operating point from getting too
out of
whack. So there\'s no \"dead band\" per se, both the small and large
signal
impedance looking in from the VG terminal always going to be something
relatively low...
Why is there no deadband? The transistors BE junction barely turn on
until there is already movement in the set point. This movement is
exactly what needs to be minimized.
If one is using one rail as a voltage reference, that\'s significant.
If, however, one is just
using the rails for power, and all signals are ground-referenced,
then it just works.
Common-mode tolerance is built into op amp designs, and at high
frequency the
capacitors handle it, while at low frequency the high differential gain
dominates the tiny common-mode effect.

It is a matter of designing the circuitry to tolerate a bit of
variance in the raw supply
voltage absolute values, while removing the irritations that come
from trying
to use a negative power rail as signal ground. In the worst case, one
can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If,
however, one is just using the rails for power, and all signals are
ground-referenced, then it just works\".  The problem is it doesn\'t
work.  See my simulation in the previous post.  It not just doesn\'t
work, it doesn\'t work *horribly* with 1.4Vpp variation in the
reference output.  It\'s pointless.


For the price of two transistors, two caps, and two resistor it can sink
or source appreciable DC current from either rail while drawing zero
quiescent current

Or rather, very low quiescent current. \"Performance\" (such as it is)
doesn\'t change much if you change R1 and R2 to 10k.

 

[Ricky]

On Sunday, March 12, 2023 at 1:54:46 AM UTC-5, bitrex wrote:

On 3/11/2023 4:41 PM, Ricky wrote:
On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:
On Saturday, March 11, 2023 at 12:25:59 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 12:10:21 PM UTC-5, bitrex wrote:
On 3/9/2023 7:32 PM, Ricky wrote:
On Thursday, March 9, 2023 at 6:18:06 PM UTC-5, Lasse Langwadt Christensen wrote:

npn+pnp follower, https://imgur.com/NhlLGGc

Does your drawing need a couple of diodes? Otherwise the output would have a dead band 1.something volts wide, no?

The small-signal AC impedance looking into the virtual ground is always
fairly low, at most whatever the small-signal AC impedance of the two
caps in parallel is.

The transistors just keep the DC operating point from getting too out of
whack. So there\'s no \"dead band\" per se, both the small and large signal
impedance looking in from the VG terminal always going to be something
relatively low...
Why is there no deadband? The transistors BE junction barely turn on until there is already movement in the set point. This movement is exactly what needs to be minimized.
If one is using one rail as a voltage reference, that\'s significant. If, however, one is just
using the rails for power, and all signals are ground-referenced, then it just works.
Common-mode tolerance is built into op amp designs, and at high frequency the
capacitors handle it, while at low frequency the high differential gain
dominates the tiny common-mode effect.

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.
For the price of two transistors, two caps, and two resistor it can sink
or source appreciable DC current from either rail while drawing zero
quiescent current.

Your circuit simply doesn\'t work without the addition of two diodes. I have no use for a circuit that can\'t maintain a reference voltage to better than 1.4V. Add the diodes and it actually works. But it\'s still not great with 200 mVpp variation. That would probably do for this design, but would result in crosstalk between channels and input and output, unless I use two such circuits. Far too much bother, board space and cost. At some point, adding all the components costs as much as the components. Run the simulation.

Which two caps and two resistors can\'t do without the
bias string drawing the same DC quiescent current as the max you wanna
source or sink.

Not sure what you are talking about here. Which circuit is this, a, b, c, or d? Or did you not run the simulation?

Your LDO \"virtual ground\" can\'t sink current either, it\'s only \"sinking\"
cuz your sense divider is pulling 20 mA all day.

Yes, that\'s why the divider resistors are sized that way, which is what I said. Did you read my post? The op amp is the optimum circuit in virtually every respect. It may cost a few pennies more than the transistor design, but the transistor design won\'t fit on the board, so it\'s essentially a no-show and the cost isn\'t relevant. One op amp is used for both channels with virtually no crosstalk, just 150 uVpp on the output or -85 dB.

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

 

[whit3rd]

On Saturday, March 11, 2023 at 1:41:44 PM UTC-8, Ricky wrote:

On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.

What \'reference output\' do you refer to? There\'s no absolute ground from a class 2 wallwart,
and power rails are usually not used as reference voltages, so a volt or so variance there is
no problem. Would your car\'s electronics fail at 12V but work normally at 13.7 V? Not an
acceptable bit of circuit design, if it does. 1.4Vpp there would be within normal tolerance.

It\'s not horrible by any means, just... something you need to design for.

 

[Ricky]

On Sunday, March 12, 2023 at 4:13:25 AM UTC-4, whit3rd wrote:

On Saturday, March 11, 2023 at 1:41:44 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.
What \'reference output\' do you refer to? There\'s no absolute ground from a class 2 wallwart,
and power rails are usually not used as reference voltages, so a volt or so variance there is
no problem. Would your car\'s electronics fail at 12V but work normally at 13.7 V? Not an
acceptable bit of circuit design, if it does. 1.4Vpp there would be within normal tolerance.

The whole point of the circuit is to create a reference point for an amplifier circuit to operate with, that is midway between ground and the 12V rail.. What does \"absolute\" ground have to do with anything? There\'s no such thing as an absolute ground anyway. Ground is what you declare it to be. Here\'s what I said in the first post...

\"I read some of the discussion on \"rail splitting\" and it occurred to me that there should be a market for these devices. I am working on a design that will run op amps from a single rail and I need a 6V level, that can both source and sink current.\"

Maybe that was not clear enough. I didn\'t explicitly say the 6V would be the virtual ground of the amp circuit.

Having 1.4Vpp in the reference would muck the output by 1.4Vpp. WTF are you talking about \"normal\" tolerance? 1.4Vpp on low voltage power rail is horrid.


> It\'s not horrible by any means, just... something you need to design for.

LOL I\'m not asking you to design any amplifiers for me. I suspect the problem here is you don\'t understand the application. That\'s always the first thing any designer needs to do, is understand the application.

If you still don\'t understand the circuit, please look at the LTspice file I posted. In circuits a through c, the current injected into the reference voltage is just from a spice voltage source. In circuit d, I added an op amp that is like the stage which is driving the current that winds up in the reference. This lets me measure the total current drawn by the output stage of the amp, combined with the op amp providing the reference combined. The two currents are essentially out of phase, so create what looks like a sine wave rectified with about 2 mA of quiescent current.

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christensen]

søndag den 12. marts 2023 kl. 09.40.48 UTC+1 skrev Ricky:

On Sunday, March 12, 2023 at 4:13:25 AM UTC-4, whit3rd wrote:
On Saturday, March 11, 2023 at 1:41:44 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.

depends on what you consider to be ground

Version 4
SHEET 1 2292 1252
WIRE 160 -80 0 -80
WIRE 240 -80 160 -80
WIRE 304 -80 240 -80
WIRE 400 -80 304 -80
WIRE 1088 -80 400 -80
WIRE 160 -32 160 -80
WIRE 400 -32 400 -80
WIRE 0 -16 0 -80
WIRE 304 32 304 -80
WIRE 160 80 160 48
WIRE 240 80 160 80
WIRE 400 144 400 32
WIRE 464 144 400 144
WIRE 576 144 464 144
WIRE 704 144 576 144
WIRE 992 144 784 144
WIRE 1008 144 992 144
WIRE 1136 144 1008 144
WIRE 160 160 160 80
WIRE 304 160 304 128
WIRE 400 160 400 144
WIRE 400 160 304 160
WIRE 576 176 576 144
WIRE 1088 176 1088 -80
WIRE 304 192 304 160
WIRE 1136 192 1136 144
WIRE 1136 192 1120 192
WIRE 1008 208 1008 144
WIRE 1056 208 1008 208
WIRE 1184 224 1120 224
WIRE 160 240 160 160
WIRE 240 240 160 240
WIRE 1184 240 1184 224
WIRE 160 288 160 240
WIRE 400 288 400 160
WIRE 1184 336 1184 320
WIRE 0 400 0 64
WIRE 160 400 160 368
WIRE 160 400 0 400
WIRE 304 400 304 288
WIRE 304 400 160 400
WIRE 400 400 400 352
WIRE 400 400 304 400
WIRE 1088 400 1088 240
WIRE 1088 400 400 400
FLAG 464 144 Out_a
FLAG 240 -80 12V_a
FLAG 160 160 Vref_a
FLAG 992 144 Vload_d
FLAG 1184 336 0
FLAG 576 176 0
SYMBOL npn 240 32 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL pnp 240 288 M180
WINDOW 0 63 33 Left 2
WINDOW 3 60 70 Left 2
SYMATTR InstName Q2
SYMATTR Value 2N3906
SYMBOL res 144 -48 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 144 272 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL cap 384 -32 R0
SYMATTR InstName C1
SYMATTR Value 3.3u
SYMATTR SpiceLine V=50 Irms=14.1 Rser=0.00348155 Lser=0 mfg=\"KEMET\" pn=\"C1210C335K5RAC\" type=\"X7R\"
SYMBOL voltage 0 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12V
SYMBOL cap 384 288 R0
SYMATTR InstName C2
SYMATTR Value 3.3u
SYMATTR SpiceLine V=50 Irms=14.1 Rser=0.00348155 Lser=0
SYMBOL res 800 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R12
SYMATTR Value 75
SYMBOL voltage 1184 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V8
SYMATTR Value SINE(0 1.32Vp 20)
SYMBOL Opamps\\\\AD824 1088 144 M0
SYMATTR InstName U3
TEXT 624 0 Left 2 !.tran 300m

 

[bitrex]

On 3/12/2023 3:07 AM, Ricky wrote:

On Sunday, March 12, 2023 at 1:54:46 AM UTC-5, bitrex wrote:
On 3/11/2023 4:41 PM, Ricky wrote:
On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:
On Saturday, March 11, 2023 at 12:25:59 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 12:10:21 PM UTC-5, bitrex wrote:
On 3/9/2023 7:32 PM, Ricky wrote:
On Thursday, March 9, 2023 at 6:18:06 PM UTC-5, Lasse Langwadt Christensen wrote:

npn+pnp follower, https://imgur.com/NhlLGGc

Does your drawing need a couple of diodes? Otherwise the output would have a dead band 1.something volts wide, no?

The small-signal AC impedance looking into the virtual ground is always
fairly low, at most whatever the small-signal AC impedance of the two
caps in parallel is.

The transistors just keep the DC operating point from getting too out of
whack. So there\'s no \"dead band\" per se, both the small and large signal
impedance looking in from the VG terminal always going to be something
relatively low...
Why is there no deadband? The transistors BE junction barely turn on until there is already movement in the set point. This movement is exactly what needs to be minimized.
If one is using one rail as a voltage reference, that\'s significant. If, however, one is just
using the rails for power, and all signals are ground-referenced, then it just works.
Common-mode tolerance is built into op amp designs, and at high frequency the
capacitors handle it, while at low frequency the high differential gain
dominates the tiny common-mode effect.

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.
For the price of two transistors, two caps, and two resistor it can sink
or source appreciable DC current from either rail while drawing zero
quiescent current.

Your circuit

\"My circuit\"?

 

[Don]

Lasse Langwadt Christensen wrote:

skrev Ricky:
whit3rd wrote:
Ricky wrote:
whit3rd wrote:

It is a matter of designing the circuitry to tolerate a bit of variance
in the raw supply voltage absolute values, while removing the irritations
that come from trying
to use a negative power rail as signal ground. In the worst case, one
can add positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however,
one is just using the rails for power, and all signals are ground-referenced,
then it just works\". The problem is it doesn\'t work. See my simulation in the
previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp
variation in the reference output. It\'s pointless.

depends on what you consider to be ground

<LTSpice code snipped>

Does your simulation serendipitously stay balanced due to its zero
voltage offset sine \"load?\"
Will an unbalanced load, with, for instance, 100 mA pulled from the
positive rail and nothing drawn from the negative rail, sink virtual
ground downward? Because, for the unbalanced case, no current flows
through Q2 to balance things out?

Danke,

--
Don, KB7RPU, https://www.qsl.net/kb7rpu
There was a young lady named Bright Whose speed was far faster than light;
She set out one day In a relative way And returned on the previous night.

 

[Lasse Langwadt Christensen]

søndag den 12. marts 2023 kl. 15.25.56 UTC+1 skrev Don:

Lasse Langwadt Christensen wrote:
skrev Ricky:
whit3rd wrote:
Ricky wrote:
whit3rd wrote:

It is a matter of designing the circuitry to tolerate a bit of variance
in the raw supply voltage absolute values, while removing the irritations
that come from trying
to use a negative power rail as signal ground. In the worst case, one
can add positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however,
one is just using the rails for power, and all signals are ground-referenced,
then it just works\". The problem is it doesn\'t work. See my simulation in the
previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp
variation in the reference output. It\'s pointless.

depends on what you consider to be ground
LTSpice code snipped

Does your simulation serendipitously stay balanced due to its zero
voltage offset sine \"load?\"
Will an unbalanced load, with, for instance, 100 mA pulled from the
positive rail and nothing drawn from the negative rail, sink virtual
ground downward? Because, for the unbalanced case, no current flows
through Q2 to balance things out?

that would just make the power supply effectively ~ +5.4V / -6.6V instead of +/-6V
which is fine

 

[Ricky]

On Sunday, March 12, 2023 at 5:19:55 AM UTC-4, Lasse Langwadt Christensen wrote:

søndag den 12. marts 2023 kl. 09.40.48 UTC+1 skrev Ricky:
On Sunday, March 12, 2023 at 4:13:25 AM UTC-4, whit3rd wrote:
On Saturday, March 11, 2023 at 1:41:44 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.
depends on what you consider to be ground

I don\'t get to choose the ground. The 12V power supply negative rail is ground, along with the 5V negative rail and the 3.3V negative rail and the -12V positive rail. This is a daughter card on a main board. Take a look at your power rails, the 12V positive and negative (you didn\'t even name the negative rail). They are bouncing 1.4Vpp. Is this the sort of amplifiers that you design???

I have no idea what you are thinking.

The transistor circuit without the diodes does nothing useful. It absolutely does not provide a stable output voltage.

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

 

[Ricky]

On Sunday, March 12, 2023 at 9:57:00 AM UTC-4, bitrex wrote:

On 3/12/2023 3:07 AM, Ricky wrote:
On Sunday, March 12, 2023 at 1:54:46 AM UTC-5, bitrex wrote:
On 3/11/2023 4:41 PM, Ricky wrote:
On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:
On Saturday, March 11, 2023 at 12:25:59 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 12:10:21 PM UTC-5, bitrex wrote:
On 3/9/2023 7:32 PM, Ricky wrote:
On Thursday, March 9, 2023 at 6:18:06 PM UTC-5, Lasse Langwadt Christensen wrote:

npn+pnp follower, https://imgur.com/NhlLGGc

Does your drawing need a couple of diodes? Otherwise the output would have a dead band 1.something volts wide, no?

The small-signal AC impedance looking into the virtual ground is always
fairly low, at most whatever the small-signal AC impedance of the two
caps in parallel is.

The transistors just keep the DC operating point from getting too out of
whack. So there\'s no \"dead band\" per se, both the small and large signal
impedance looking in from the VG terminal always going to be something
relatively low...
Why is there no deadband? The transistors BE junction barely turn on until there is already movement in the set point. This movement is exactly what needs to be minimized.
If one is using one rail as a voltage reference, that\'s significant. If, however, one is just
using the rails for power, and all signals are ground-referenced, then it just works.
Common-mode tolerance is built into op amp designs, and at high frequency the
capacitors handle it, while at low frequency the high differential gain
dominates the tiny common-mode effect.

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.
For the price of two transistors, two caps, and two resistor it can sink
or source appreciable DC current from either rail while drawing zero
quiescent current.

Your circuit
\"My circuit\"?

I guess it\'s Lasse\'s circuit. Either way, it doesn\'t work. It\'s pointless.

--

Rick C.

+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209

 

[bitrex]

On 3/12/2023 10:25 AM, Don wrote:

Lasse Langwadt Christensen wrote:
skrev Ricky:
whit3rd wrote:
Ricky wrote:
whit3rd wrote:

It is a matter of designing the circuitry to tolerate a bit of variance
in the raw supply voltage absolute values, while removing the irritations
that come from trying
to use a negative power rail as signal ground. In the worst case, one
can add positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however,
one is just using the rails for power, and all signals are ground-referenced,
then it just works\". The problem is it doesn\'t work. See my simulation in the
previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp
variation in the reference output. It\'s pointless.

depends on what you consider to be ground

LTSpice code snipped

Does your simulation serendipitously stay balanced due to its zero
voltage offset sine \"load?\"
Will an unbalanced load, with, for instance, 100 mA pulled from the
positive rail and nothing drawn from the negative rail, sink virtual
ground downward? Because, for the unbalanced case, no current flows
through Q2 to balance things out?

Danke,

It has poor DC regulation, unless you regulate it. But it won\'t rail
nearly as bad as just two caps and two resistors will if you try to draw
more unbalanced DC current from that than the latter\'s voltage divider
can support.

That is to say if regulation needs to not suck for large signals at 20
Hz as in his sim then the +/- rails created need to be post-regulated.

Like what kind of performance do y\'all expect for two transistors, lol.
Many applications that split a wall-wart will post-regulate the +/-
rails which resolves its problems as a virtual ground at DC pretty well
as far as the rest of the circuit is concerned.

 

[Ricky]

On Sunday, March 12, 2023 at 1:49:28 PM UTC-4, bitrex wrote:

On 3/12/2023 10:25 AM, Don wrote:
Lasse Langwadt Christensen wrote:
skrev Ricky:
whit3rd wrote:
Ricky wrote:
whit3rd wrote:

It is a matter of designing the circuitry to tolerate a bit of variance
in the raw supply voltage absolute values, while removing the irritations
that come from trying
to use a negative power rail as signal ground. In the worst case, one
can add positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however,
one is just using the rails for power, and all signals are ground-referenced,
then it just works\". The problem is it doesn\'t work. See my simulation in the
previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp
variation in the reference output. It\'s pointless.

depends on what you consider to be ground

LTSpice code snipped

Does your simulation serendipitously stay balanced due to its zero
voltage offset sine \"load?\"
Will an unbalanced load, with, for instance, 100 mA pulled from the
positive rail and nothing drawn from the negative rail, sink virtual
ground downward? Because, for the unbalanced case, no current flows
through Q2 to balance things out?

Danke,

It has poor DC regulation, unless you regulate it. But it won\'t rail
nearly as bad as just two caps and two resistors will if you try to draw
more unbalanced DC current from that than the latter\'s voltage divider
can support.

That is to say if regulation needs to not suck for large signals at 20
Hz as in his sim then the +/- rails created need to be post-regulated.

Why on earth do you think the power rail needs to be regulated??? It\'s already regulated to 12V. The idea is to provide a regulated 6V that handles both + and - current.

Like what kind of performance do y\'all expect for two transistors, lol.
Many applications that split a wall-wart will post-regulate the +/-
rails which resolves its problems as a virtual ground at DC pretty well
as far as the rest of the circuit is concerned.

Two transistors with the diodes, actually works fairly well. If the circuit were driving off a zener diode to the common point of the two diodes, it would regulate much better than 200 mV. Or the resistors can be reduced in size, but that adds idle current that is not desirable. Actually, the zener would probably not do anything better without the resistors being reduced as well. The point is the bases need some minimum current to drive the output current through the CE. The zener doesn\'t reduce the need for drive current, it just holds the reference voltage more stable as the base current changes. Rather than the resistor currents changing, the diode currents change, driving the zener.

--

Rick C.

++- Get 1,000 miles of free Supercharging
++- Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christensen]

søndag den 12. marts 2023 kl. 18.29.26 UTC+1 skrev Ricky:

On Sunday, March 12, 2023 at 9:57:00 AM UTC-4, bitrex wrote:
On 3/12/2023 3:07 AM, Ricky wrote:
On Sunday, March 12, 2023 at 1:54:46 AM UTC-5, bitrex wrote:
On 3/11/2023 4:41 PM, Ricky wrote:
On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:
On Saturday, March 11, 2023 at 12:25:59 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 12:10:21 PM UTC-5, bitrex wrote:
On 3/9/2023 7:32 PM, Ricky wrote:
On Thursday, March 9, 2023 at 6:18:06 PM UTC-5, Lasse Langwadt Christensen wrote:

npn+pnp follower, https://imgur.com/NhlLGGc

Does your drawing need a couple of diodes? Otherwise the output would have a dead band 1.something volts wide, no?

The small-signal AC impedance looking into the virtual ground is always
fairly low, at most whatever the small-signal AC impedance of the two
caps in parallel is.

The transistors just keep the DC operating point from getting too out of
whack. So there\'s no \"dead band\" per se, both the small and large signal
impedance looking in from the VG terminal always going to be something
relatively low...
Why is there no deadband? The transistors BE junction barely turn on until there is already movement in the set point. This movement is exactly what needs to be minimized.
If one is using one rail as a voltage reference, that\'s significant. If, however, one is just
using the rails for power, and all signals are ground-referenced, then it just works.
Common-mode tolerance is built into op amp designs, and at high frequency the
capacitors handle it, while at low frequency the high differential gain
dominates the tiny common-mode effect.

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.
For the price of two transistors, two caps, and two resistor it can sink
or source appreciable DC current from either rail while drawing zero
quiescent current.

Your circuit
\"My circuit\"?
I guess it\'s Lasse\'s circuit. Either way, it doesn\'t work. It\'s pointless..

maybe in your application

if you need a reference that can sink and source, not a virtual ground then only thing that will work
is two resistors and an opamp

 

[whit3rd]

On Sunday, March 12, 2023 at 10:27:40 AM UTC-7, Ricky wrote:

On Sunday, March 12, 2023 at 5:19:55 AM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 12. marts 2023 kl. 09.40.48 UTC+1 skrev Ricky:
On Sunday, March 12, 2023 at 4:13:25 AM UTC-4, whit3rd wrote:
On Saturday, March 11, 2023 at 1:41:44 PM UTC-8, Ricky wrote:
On Saturday, March 11, 2023 at 3:51:23 PM UTC-5, whit3rd wrote:

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply
voltage absolute values, while removing the irritations that come from trying
to use a negative power rail as signal ground. In the worst case, one can add
positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, \"If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works\". The problem is it doesn\'t work. See my simulation in the previous post. It not just doesn\'t work, it doesn\'t work *horribly* with 1.4Vpp variation in the reference output. It\'s pointless.
depends on what you consider to be ground
I don\'t get to choose the ground. The 12V power supply negative rail is ground, along with the 5V negative rail and the 3.3V negative rail and the -12V positive rail. This is a daughter card on a main board. Take a look at your power rails, the 12V positive and negative (you didn\'t even name the negative rail). They are bouncing 1.4Vpp. Is this the sort of amplifiers that you design???

What does the variance of power rails do to a transimpedance amplifier? Nothing, really. There\'s
an input current, an operational amplifier, and a resistor in feedback... as long as you can take out
a signal wire and make a ground connection, the power solution with two transistors DOES work.
There\'s no significant problem with power rails there.

If power rails \'bounce\', so what? In most of my work, a bunch of boxes all route signals
for various operations, and sometimes I want a variant of one of those boxes... so a single-voltage
wall wart and a few parts go into the new unit.

I have no idea what you are thinking.

The transistor circuit without the diodes does nothing useful. It absolutely does not provide a stable output voltage.

It certainly does something useful; that TIA won\'t have a lack of power. What OTHER requirements you
might want to satisfy, we have no clue to.