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Hmm 4MB/s is very slow for PCI.
Hmm 60-70 MB/s would be a very reasonable speed. I would be happy witHmm 4MB/s is very slow for PCI.
As above (/below) it's reasonable target performance, no x86 system
allows you to burst to a target card (seems ridiculous but is the case).
If you want better PCI performance you have to have master functionality
on your plug in card.
Maximum performance depends you your PC architecture and what else is
plugged into your PCI bus. I believe that 60-70 MB/s is considered
a reasonable result for real world systems.
Nial.
No, all transactions have to me mastered by the plug in card.Hmm 60-70 MB/s would be a very reasonable speed. I would be happy with
40-50MB/s. DO you mean. to achive that speed i would have to use the PCI
master of my PCI card to read and write data from/to the x86 or send data
from the x86 to the card with the PC as a master and send data from the PCI
board to the x86 with the PCI board as a master?
Actually it is not. Like others pointed out: most x86 can't initiateOn Sep 13, 7:02=A0pm, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com
wrote:
Hmm, you have used it. can you give me some help please? I can't
understa=
nt
some points of documentations. I am planing on use it with a 32 bits
WB.
But i could not understand the =A0bytes lane table at implementation
sect=
ion.
Unfortunately I don't have the VHDL code in front of me to remind me
of exactly how I connected up the wishbone side, but for me I was
using 32-bit registers, and for that using the core was pretty
straightforward.
Which was the max speed with PCI32lite you could achive?
I was getting a little over a cycle a micro second iirc. So that's a
little over 4MB/s.
Which driver you
are using? I will run my card on a linux system too.
I wrote my own driver from scratch.
But was you able to
perform burst writes?
I didn't need burst writes and so didn't try. But I don't think you
will be able to do that with the pci32lite core - it's pretty basic,
fine for simple reading/writing to registers but not suitable for
higher performance data transfer. For that Master functionality is
needed.
Hmm 4MB/s is very slow for PCI. Can you send me your driver file? I got
"Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
On Sep 13, 7:02=A0pm, "Sink0
sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com
wrote:
Hmm, you have used it. can you give me some help please? I can't
understa=
nt
some points of documentations. I am planing on use it with a 32 bits
WB.
But i could not understand the =A0bytes lane table at implementation
sect=
ion.
Unfortunately I don't have the VHDL code in front of me to remind me
of exactly how I connected up the wishbone side, but for me I was
using 32-bit registers, and for that using the core was pretty
straightforward.
Which was the max speed with PCI32lite you could achive?
I was getting a little over a cycle a micro second iirc. So that's a
little over 4MB/s.
Which driver you
are using? I will run my card on a linux system too.
I wrote my own driver from scratch.
But was you able to
perform burst writes?
I didn't need burst writes and so didn't try. But I don't think you
will be able to do that with the pci32lite core - it's pretty basic,
fine for simple reading/writing to registers but not suitable for
higher performance data transfer. For that Master functionality is
needed.
Hmm 4MB/s is very slow for PCI. Can you send me your driver file? I got
Actually it is not. Like others pointed out: most x86 can't initiate
burst mode. The PCI card has to initiate burst mode. If the card
cannot do that you'll see the PCI bus has a lot of overhead for single
32bit transfers.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
DMA is something you should forget when talking about PCI. PCI is"Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
On Sep 13, 7:02=A0pm, "Sink0"
sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com
wrote:
Hmm, you have used it. can you give me some help please? I can't
understa=
nt
some points of documentations. I am planing on use it with a 32 bits
WB.
But i could not understand the =A0bytes lane table at implementation
sect=
ion.
Unfortunately I don't have the VHDL code in front of me to remind me
of exactly how I connected up the wishbone side, but for me I was
using 32-bit registers, and for that using the core was pretty
straightforward.
Which was the max speed with PCI32lite you could achive?
I was getting a little over a cycle a micro second iirc. So that's a
little over 4MB/s.
Which driver you
are using? I will run my card on a linux system too.
I wrote my own driver from scratch.
But was you able to
perform burst writes?
I didn't need burst writes and so didn't try. But I don't think you
will be able to do that with the pci32lite core - it's pretty basic,
fine for simple reading/writing to registers but not suitable for
higher performance data transfer. For that Master functionality is
needed.
Hmm 4MB/s is very slow for PCI. Can you send me your driver file? I got
Actually it is not. Like others pointed out: most x86 can't initiate
burst mode. The PCI card has to initiate burst mode. If the card
cannot do that you'll see the PCI bus has a lot of overhead for single
32bit transfers.
Hmm but if initiate burst with my card, will x86 be able to handle it or i
need to make use DMA? And what would be the benefit of using PCI instead of
USB2.0? If i use a chip like PLX PCI 9030 will i be able to achive high
speed at PCI bus?
That was a very useful piece of information. But explain me something. LetDMA is something you should forget when talking about PCI. PCI is
about pushing or pulling blocks of data between a master and a slave.
For some reason a PC cannot pull a block of data from a PCI card so
the PCI card needs to be capable of becoming a master and push data
into the PC's memory.
The driver needs to allocate a piece of fixed non-swappable memory and
get the physical address from the OS. The driver sets this address and
the number of bytes to transfer in the PCI card's registers. After
this, the PCI card can write (push) the data into the PC's memory.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
The PCI card is supposed to generate an interrupt when the transfer isDMA is something you should forget when talking about PCI. PCI is
about pushing or pulling blocks of data between a master and a slave.
For some reason a PC cannot pull a block of data from a PCI card so
the PCI card needs to be capable of becoming a master and push data
into the PC's memory.
The driver needs to allocate a piece of fixed non-swappable memory and
get the physical address from the OS. The driver sets this address and
the number of bytes to transfer in the PCI card's registers. After
this, the PCI card can write (push) the data into the PC's memory.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
That was a very useful piece of information. But explain me something. Let
supose a situation. PC write data to PCI card. After a while PCI card
become master of the bus and send a burst of data to PC. Lets say we are
using Linux OS. TO send and read data to/from the PCI card its
straigtfoward using the functions read and write memory. But considering
the PCI card as a master, how am i going to read that data at the PC side?
With the same read memory function does not seens the most intuitive answer
becouse i supose the read memory function would be associated to a PCI
transaction with a CBE pins pattern.
Thank you very much. You are helping a lot!!. I am designing the driveThe PCI card is supposed to generate an interrupt when the transfer is
finished. The driver which handles the interrupts knows that all the
data is written in the buffer and can start processing the data.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
Using a Virtex-5 with a x1 PCIe interface (Xilinx ML506 board) using theHmm 4MB/s is very slow for PCI.
As above (/below) it's reasonable target performance, no x86 system
allows you to burst to a target card (seems ridiculous but is the case).
If you want better PCI performance you have to have master functionality
on your plug in card.
Maximum performance depends you your PC architecture and what else is
plugged into your PCI bus. I believe that 60-70 MB/s is considered
a reasonable result for real world systems.
Nial.
Hmm 60-70 MB/s would be a very reasonable speed. I would be happy with
40-50MB/s. DO you mean. to achive that speed i would have to use the PCI
master of my PCI card to read and write data from/to the x86 or send data
from the x86 to the card with the PC as a master and send data from the PCI
board to the x86 with the PCI board as a master? I am just curious, whats
speed is achivable with a x1 PCI express bus? Any idea?
They can if you mark the memory write combining.I have used the pci32lite in a Spartan 3. What I found was that:
(1) I couldn't get it to do burst reads, because surprisingly, the PC
doesn't do burst reads. At least that was the conclusion I came to
after googling to find out why my linux driver was breaking up burst
requests into individual transactions. If you want to do burst reads,
you need master functionality in the PCI IP. Also, iirc, pci32lite
documentation indicated that it "supports" burst mode by signaling to
the host system that bursts need to be broken into individually
transactions.
AFAIK no x86 based machines will drive burst accesses to plug in
cards.
On 09/13/2010 09:30 AM, Nial Stewart wrote:
I have used the pci32lite in a Spartan 3. What I found was that:
(1) I couldn't get it to do burst reads, because surprisingly, the PC
doesn't do burst reads. At least that was the conclusion I came to
after googling to find out why my linux driver was breaking up burst
requests into individual transactions. If you want to do burst reads,
you need master functionality in the PCI IP. Also, iirc, pci32lite
documentation indicated that it "supports" burst mode by signaling to
the host system that bursts need to be broken into individually
transactions.
AFAIK no x86 based machines will drive burst accesses to plug in
cards.
They can if you mark the memory write combining.
-hpa
Hi,On 09/13/2010 09:30 AM, Nial Stewart wrote:
I have used the pci32lite in a Spartan 3. What I found was that:
(1) I couldn't get it to do burst reads, because surprisingly, the PC
doesn't do burst reads. At least that was the conclusion I came to
after googling to find out why my linux driver was breaking up burst
requests into individual transactions. If you want to do burst reads,
you need master functionality in the PCI IP. Also, iirc, pci32lite
documentation indicated that it "supports" burst mode by signaling to
the host system that bursts need to be broken into individually
transactions.
AFAIK no x86 based machines will drive burst accesses to plug in
cards.
They can if you mark the memory write combining.
-hpa
But is wirite combining reliable? All i have reared is that lots of problem
can happens.
Sink
---------------------------------------
Posted throughhttp://www.FPGARelated.com
In the PCI bus respect, I thought Altera was a loser.
4. The same design using Flex 20K by Altera got about 56MHz running
frequency, and I had to spend 1 week to manually layout to get it over
66.7MHz. All critical paths are IRDY and TRDY.
5. The same design using Virtex II by Xilinx usually got 67MHz or
above running frequency after first compilation.
1. The chip switch from Flex 20K to Virtex II occurs in 2003. At thatIn the PCI bus respect, I thought Altera was a loser.
In Altera's defence this must have been a good few years ago, the Flex devices
haven't been 'current' for a while.
And comparing a flex device with a Virtex you're comparing a low cost
device with a much more expensive part!
These days I'd expect _any_ FPGA to fairly easily meet 33MHz 32 Bits and
any current Stratix or Virtex to meet 66MHz 64 Bits.
Nial.
Chip prices are greatly affected by the process generation in two1. The chip switch from Flex 20K to Virtex II occurs in 2003. At that
time, I thought both were at the same level of technology. And I heard
that the price of Virtex II -1000 was even lower than Flex 20K's at
the time. Maybe there was a promotion selling scheme behind the door
by Xilinx to encourage customers to switch to its products.
As you say, for some designs frequency is paramount. But this is not2. Running frequency is a lifeline: death or live. No matter how good
your design is, when it fails to reach the specified running
frequency, all is dead. When redesigning with a new military product,
the LUT space usage in Virtex II was above 93%. At that time, one can
imagine that if everything went well except the running frequency, the
product board had to be redesigned, chips had to be reselected and
deadline would be rescheduled and a big penalty was pending.
fortuitously after several fine tuning of compilation parameters,
using Xilinx ISE 8.x, it passed the 66.7MHz running frequency, but it
never passed above 66.7MHz using Xlinx ISE 9.x when a colleague tried
to confirm the running frequency using the latest version of ISE 9.x.
Again, this is a software issue as well. Unless you have tested your3. The PCI legacy circuits from both Altera and Xilinx go into their
advanced structures of their next generations, but the shortcoming
with Altera handling PCI bus method doesn't go away as you claim. It
costs a lot of route resources to get the 66MHz. When LUT space is
being used up, the problem will pop up and goes after you.
AFAIK this function is performed by a special logic cell in the FPGAXilinx cores make use of special features of certain pins on the
device with names like IRDY and TRDY that have some built-in logic to speed up the
combinatorial PCI requirements. I don't think the synthesis tools support these
functions directly.
Maybe, but then you have to properly use the UCF constraint system,However the FPGA's have been getting faster, so you may not need
the extra stunt hardware to meet PCI timing anymore.
"At that time I believe theOn Sep 10, 10:49 pm, Gabor <ga...@alacron.com> wrote:
Xilinx cores make use of special features of certain pins on the
device with names like IRDY and TRDY that have some built-in logic to speed up the
combinatorial PCI requirements. I don't think the synthesis tools support these
functions directly.
AFAIK this function is performed by a special logic cell in the FPGA
called PCILOGIC on Spartan 2 and PCILOGICSE on Spartan 3E/6, with
dedicated routing to the I/Os. To make the those cells appear in FPGA
Editor (they don't by default, apparently Xilinx don't want you to use
them), enter in the FPGA Editor command line (the white text box at
the bottom of the window):
select site *PCI*
add
I guess you can instantiate those primitives in the HDL and the P&R
tool will nicely use the dedicated I/O routing channels.
However the FPGA's have been getting faster, so you may not need
the extra stunt hardware to meet PCI timing anymore.
Maybe, but then you have to properly use the UCF constraint system,
which is another evil =]
S.
Ok, but the fact remains that you are judging these two companies onOn Sep 17, 3:32 pm, Sebastien Bourdeauducq
sebastien.bourdeaud...@gmail.com> wrote:
On Sep 10, 10:49 pm, Gabor <ga...@alacron.com> wrote:
Xilinx cores make use of special features of certain pins on the
device with names like IRDY and TRDY that have some built-in logic to speed up the
combinatorial PCI requirements. I don't think the synthesis tools support these
functions directly.
AFAIK this function is performed by a special logic cell in the FPGA
called PCILOGIC on Spartan 2 and PCILOGICSE on Spartan 3E/6, with
dedicated routing to the I/Os. To make the those cells appear in FPGA
Editor (they don't by default, apparently Xilinx don't want you to use
them), enter in the FPGA Editor command line (the white text box at
the bottom of the window):
select site *PCI*
add
I guess you can instantiate those primitives in the HDL and the P&R
tool will nicely use the dedicated I/O routing channels.
However the FPGA's have been getting faster, so you may not need
the extra stunt hardware to meet PCI timing anymore.
Maybe, but then you have to properly use the UCF constraint system,
which is another evil =]
S.
"At that time I believe the
older Altera parts were still being designed using MAX+PLUS II. I
can
personally verify that this software was a total dog for getting good
speed results. They eventually switched all their parts over to
Quartus which gives much better results. "
The claim is false. I used Quartus 4.x at that time.
"Do you mean Apex20K? That was released in 1998, I can't find the date
for
the Virtex II release but it was 2001/2002 I think which makes it the
next
generation of devices. "
Yes. Apex 20K. Virtex II release Document mentioned date: V1.1
December 6, 2000.
At the time both were top products for their companies.
Weng