T
Tricky
Guest
Im trying to replace an altsyncram instatiation with an implied
version, and I cant figure it out atm - thought Id put it out as a
little challenge.
Heres the altsyncram (dual clocked, in and out port width difference):
alt_ram : altsyncram
generic map (
Width_a => 64,
width_b => 16,
widthad_a => 7,
widthad_b => 9
)
port map (
clock0 => clka,
clock1 => clkb,
data_a => data_a,
address_a => std_logic_vector(to_unsigned(addr_a, 7) ),
address_b => std_logic_vector(to_unsigned(addr_b, 9) ),
q_b => q_b
);
Its easy to infer it when A and B ports are identical widths, bit how
to do it now there is a width mismatch?
version, and I cant figure it out atm - thought Id put it out as a
little challenge.
Heres the altsyncram (dual clocked, in and out port width difference):
alt_ram : altsyncram
generic map (
Width_a => 64,
width_b => 16,
widthad_a => 7,
widthad_b => 9
)
port map (
clock0 => clka,
clock1 => clkb,
data_a => data_a,
address_a => std_logic_vector(to_unsigned(addr_a, 7) ),
address_b => std_logic_vector(to_unsigned(addr_b, 9) ),
q_b => q_b
);
Its easy to infer it when A and B ports are identical widths, bit how
to do it now there is a width mismatch?