Quartus Inference Challenge

T

Tricky

Guest
Im trying to replace an altsyncram instatiation with an implied
version, and I cant figure it out atm - thought Id put it out as a
little challenge.
Heres the altsyncram (dual clocked, in and out port width difference):

alt_ram : altsyncram
generic map (
Width_a => 64,
width_b => 16,

widthad_a => 7,
widthad_b => 9

)
port map (

clock0 => clka,
clock1 => clkb,

data_a => data_a,
address_a => std_logic_vector(to_unsigned(addr_a, 7) ),

address_b => std_logic_vector(to_unsigned(addr_b, 9) ),
q_b => q_b

);


Its easy to infer it when A and B ports are identical widths, bit how
to do it now there is a width mismatch?
 
On Tue, 19 May 2009 10:15:00 -0700 (PDT), Tricky wrote:

Its easy to infer it when A and B ports are identical widths, bit how
to do it now there is a width mismatch?
In a recent thread on comp.arch.fpga, various posts pointed
out that this can't currently be done for Xilinx BRAMs using
any of the usual synthesis tools. I strongly suspect it can't
be done for Altera either.

I tried resizing "by hand" in the VHDL but couldn't make it
work properly. Might try again later in Verilog, where it's
easier to do the shared-variable thing.
--
Jonathan Bromley, Consultant

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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On May 19, 6:15 pm, Tricky <Trickyh...@gmail.com> wrote:
Im trying to replace an altsyncram instatiation with an implied
version, and I cant figure it out atm - thought Id put it out as a
little challenge.
Heres the altsyncram (dual clocked, in and out port width difference):

alt_ram : altsyncram
  generic map (
    Width_a    => 64,
    width_b    => 16,

    widthad_a  => 7,
    widthad_b  => 9

  )
  port map (

    clock0         => clka,
    clock1         => clkb,

    data_a         => data_a,
    address_a      => std_logic_vector(to_unsigned(addr_a, 7) ),

    address_b      => std_logic_vector(to_unsigned(addr_b, 9) ),
    q_b            => q_b

  );

Its easy to infer it when A and B ports are identical widths, bit how
to do it now there is a width mismatch?
Try multiplexing a 64 bit output port into 4*16 using two address
bits. This makes the same port widths.

cheers jacko
 
On 20 May, 16:15, Jacko <jackokr...@gmail.com> wrote:
On May 19, 6:15 pm, Tricky <Trickyh...@gmail.com> wrote:



Im trying to replace an altsyncram instatiation with an implied
version, and I cant figure it out atm - thought Id put it out as a
little challenge.
Heres the altsyncram (dual clocked, in and out port width difference):

alt_ram : altsyncram
  generic map (
    Width_a    => 64,
    width_b    => 16,

    widthad_a  => 7,
    widthad_b  => 9

  )
  port map (

    clock0         => clka,
    clock1         => clkb,

    data_a         => data_a,
    address_a      => std_logic_vector(to_unsigned(addr_a, 7) ),

    address_b      => std_logic_vector(to_unsigned(addr_b, 9) ),
    q_b            => q_b

  );

Its easy to infer it when A and B ports are identical widths, bit how
to do it now there is a width mismatch?

Try multiplexing a 64 bit output port into 4*16 using two address
bits. This makes the same port widths.

cheers jacko
Yup, I can do that, but its not as efficient as the direct
instantiation.

Altera have come back saying they dont support it - I shall put in an
enhancement request.
 
Tricky wrote:

Yup, I can do that, but its not as efficient as the direct
instantiation.
But it is portable.
Does the instance use zero LUTs for the mux?

-- Mike Treseler
 
On May 20, 7:18 pm, Mike Treseler <mtrese...@gmail.com> wrote:
Tricky wrote:
Yup, I can do that, but its not as efficient as the direct
instantiation.

But it is portable.
Does the instance use zero LUTs for the mux?

     -- Mike Treseler
Probly not. Good job he didn't want the write bus smaller width, and
write before read!

cheers jacko

http://nibz.googlecode.com version G-spot
 

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