QFN packages and layout on crowded PCBs...

[Ed Lee]

On Saturday, October 22, 2022 at 12:34:16 PM UTC-7, John Larkin wrote:

On Sat, 22 Oct 2022 11:41:38 -0700 (PDT), Ed Lee
edward....@gmail.com> wrote:

On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip.. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
That will be labor intensive and will lift the chip off the board,
with solderability issues.

Another small Flex-PCB with thermal pad on one side only?

 

[Dimiter_Popoff]

On 10/22/2022 22:31, Ed Lee wrote:

On Saturday, October 22, 2022 at 12:27:08 PM UTC-7, Dimiter Popoff wrote:
On 10/22/2022 21:41, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

Depends on how many pins/pads are routed. Plugged vias on the signal pads are also possible.

Well he said it at the beginning, it is something like 3x4mm or was
it 4x5. Either way, a 0.2mm hole via with a 0.1mm annular ring is
small but how many can you fit under this. At 0.5mm pitch putting
such vias inside the signal pads is not doable even at 4 mil and
he is doing 6. I have not explored 0.1mm hole with 0.1mm annular
ring (i.e. 4 mil), looks doable, but the pcb makers go into their
\"special\" options for that sort of thing.

 

[Ricky]

On Saturday, October 22, 2022 at 3:30:39 PM UTC-4, John Larkin wrote:

On Sat, 22 Oct 2022 10:22:38 -0700 (PDT), Ed Lee
edward....@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:20:42 AM UTC-7, John Larkin wrote:
On Sat, 22 Oct 2022 10:16:12 -0700 (PDT), Ed Lee
edward....@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?

How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
A pcb thermal pad smaller than the pad on the part invites shorts to
vias.

That\'s what blind vias are for.
We\'re designing a small, super dense board right now and blind+buried
vias were suggested. Sounds tricky to me. One problem is routing out
of a big Zynq 0.8 mm BGA. The cost of two more board layers is about a
wash with blind/buried.

You can\'t probe or hack a buried via.

That shouldn\'t matter. The trace has to make it to a surface layer at some point. Probe it there. I\'ve been asked to provide more test points on this board. The chips were on the bottom, so they could not be probed directly. I\'m going to reverse that. That puts the SM connectors on the opposite side which I thought would be a bad idea. I thought they would prefer all small passives on one side and the large parts on the other. The small passives don\'t fall off the bottom in reflow. But I was told the chips don\'t either. So it doesn\'t matter which side the large parts are on.

But in this case, a surface pad still needs a surface via, and that
still collides with the power pad.

Tiny via-in-pad is a possibility for a QFN, but that could get nasty
too.

All these problems can be solved by applying money.

I have an option of the TSSOP and that is likely what I will use for one device. Another device is QFN or take a hike! There I will need to work around the space issue. It\'s not that the QFN is worse than the TSSOP it\'s replacing. It\'s just no better. I don\'t get why people like them. Or maybe they don\'t and the manufacturers are the ones pushing them! I know TI has a lot of parts with no alternative packaging.

The only real issue with the TSSOP is the availability, but I don\'t think the QFN is really any better. Sometimes there\'s just no options. Fortunately, I have parts in inventory to get started.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[Ricky]

On Saturday, October 22, 2022 at 3:41:35 PM UTC-4, Dimiter Popoff wrote:

On 10/22/2022 22:31, Ed Lee wrote:
On Saturday, October 22, 2022 at 12:27:08 PM UTC-7, Dimiter Popoff wrote:
On 10/22/2022 21:41, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

Depends on how many pins/pads are routed. Plugged vias on the signal pads are also possible.
Well he said it at the beginning, it is something like 3x4mm or was
it 4x5. Either way, a 0.2mm hole via with a 0.1mm annular ring is
small but how many can you fit under this. At 0.5mm pitch putting
such vias inside the signal pads is not doable even at 4 mil and
he is doing 6. I have not explored 0.1mm hole with 0.1mm annular
ring (i.e. 4 mil), looks doable, but the pcb makers go into their
\"special\" options for that sort of thing.

Via in pad would need to be a micro via. The pad pitch is 0.5 mm and the width is 0.28 mm. I\'m not looking to make my life difficult. Some parts have 0.4 mm pad pitch.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

 

[John Walliker]

On Sunday, 23 October 2022 at 00:09:21 UTC+1, Ricky wrote:

On Saturday, October 22, 2022 at 3:41:35 PM UTC-4, Dimiter Popoff wrote:
On 10/22/2022 22:31, Ed Lee wrote:
On Saturday, October 22, 2022 at 12:27:08 PM UTC-7, Dimiter Popoff wrote:
On 10/22/2022 21:41, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads.. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip.. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\".. Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

Depends on how many pins/pads are routed. Plugged vias on the signal pads are also possible.
Well he said it at the beginning, it is something like 3x4mm or was
it 4x5. Either way, a 0.2mm hole via with a 0.1mm annular ring is
small but how many can you fit under this. At 0.5mm pitch putting
such vias inside the signal pads is not doable even at 4 mil and
he is doing 6. I have not explored 0.1mm hole with 0.1mm annular
ring (i.e. 4 mil), looks doable, but the pcb makers go into their
\"special\" options for that sort of thing.
Via in pad would need to be a micro via. The pad pitch is 0.5 mm and the width is 0.28 mm. I\'m not looking to make my life difficult. Some parts have 0.4 mm pad pitch.

One advantage of QFN is that there are no leads to get bent in production.

John

 

[John Larkin]

On Sun, 23 Oct 2022 03:46:00 -0700 (PDT), John Walliker
<jrwalliker@gmail.com> wrote:

On Sunday, 23 October 2022 at 00:09:21 UTC+1, Ricky wrote:
On Saturday, October 22, 2022 at 3:41:35 PM UTC-4, Dimiter Popoff wrote:
On 10/22/2022 22:31, Ed Lee wrote:
On Saturday, October 22, 2022 at 12:27:08 PM UTC-7, Dimiter Popoff wrote:
On 10/22/2022 21:41, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

Depends on how many pins/pads are routed. Plugged vias on the signal pads are also possible.
Well he said it at the beginning, it is something like 3x4mm or was
it 4x5. Either way, a 0.2mm hole via with a 0.1mm annular ring is
small but how many can you fit under this. At 0.5mm pitch putting
such vias inside the signal pads is not doable even at 4 mil and
he is doing 6. I have not explored 0.1mm hole with 0.1mm annular
ring (i.e. 4 mil), looks doable, but the pcb makers go into their
\"special\" options for that sort of thing.
Via in pad would need to be a micro via. The pad pitch is 0.5 mm and the width is 0.28 mm. I\'m not looking to make my life difficult. Some parts have 0.4 mm pad pitch.

One advantage of QFN is that there are no leads to get bent in production.

John

Bent leads basically don\'t happen with a decent surface-mount process,
even semi-auto or even manual. You just need the right equipment,
which is very modest for manual placement.

We just ordered a new Yamaha p+p machine. It looks cool in the Youtube
vids. Maybe they will throw in a piano or a motorcycle or something.

 

[Dimiter_Popoff]

On 10/23/2022 18:06, John Larkin wrote:

On Sun, 23 Oct 2022 03:46:00 -0700 (PDT), John Walliker
jrwalliker@gmail.com> wrote:

On Sunday, 23 October 2022 at 00:09:21 UTC+1, Ricky wrote:
On Saturday, October 22, 2022 at 3:41:35 PM UTC-4, Dimiter Popoff wrote:
On 10/22/2022 22:31, Ed Lee wrote:
On Saturday, October 22, 2022 at 12:27:08 PM UTC-7, Dimiter Popoff wrote:
On 10/22/2022 21:41, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

Depends on how many pins/pads are routed. Plugged vias on the signal pads are also possible.
Well he said it at the beginning, it is something like 3x4mm or was
it 4x5. Either way, a 0.2mm hole via with a 0.1mm annular ring is
small but how many can you fit under this. At 0.5mm pitch putting
such vias inside the signal pads is not doable even at 4 mil and
he is doing 6. I have not explored 0.1mm hole with 0.1mm annular
ring (i.e. 4 mil), looks doable, but the pcb makers go into their
\"special\" options for that sort of thing.
Via in pad would need to be a micro via. The pad pitch is 0.5 mm and the width is 0.28 mm. I\'m not looking to make my life difficult. Some parts have 0.4 mm pad pitch.

One advantage of QFN is that there are no leads to get bent in production.

John

Bent leads basically don\'t happen with a decent surface-mount process,
even semi-auto or even manual. You just need the right equipment,
which is very modest for manual placement.

I suppose qfn is about thermal contact with the PCB, too much of a pain
to use for no other good reason. We have used a tiny qfn MOSFET driver
for switchers, works fine and having just a few signals not a
pain to route. The Ethernet PHY we use in qfn OTOH has been a real pain
to deal with a few times when it needed rework. Out of the initial
good soldering it has been OK, just unnoticeable.

We just ordered a new Yamaha p+p machine. It looks cool in the Youtube
vids. Maybe they will throw in a piano or a motorcycle or something.

So your boards will be forming bands and motorcycle to gigs, not the
worst thing to happen .

 

[Phil Hobbs]

John Larkin wrote:

On Sun, 23 Oct 2022 03:46:00 -0700 (PDT), John Walliker
jrwalliker@gmail.com> wrote:

On Sunday, 23 October 2022 at 00:09:21 UTC+1, Ricky wrote:
On Saturday, October 22, 2022 at 3:41:35 PM UTC-4, Dimiter Popoff wrote:
On 10/22/2022 22:31, Ed Lee wrote:
On Saturday, October 22, 2022 at 12:27:08 PM UTC-7, Dimiter Popoff wrote:
On 10/22/2022 21:41, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

Depends on how many pins/pads are routed. Plugged vias on the signal pads are also possible.
Well he said it at the beginning, it is something like 3x4mm or was
it 4x5. Either way, a 0.2mm hole via with a 0.1mm annular ring is
small but how many can you fit under this. At 0.5mm pitch putting
such vias inside the signal pads is not doable even at 4 mil and
he is doing 6. I have not explored 0.1mm hole with 0.1mm annular
ring (i.e. 4 mil), looks doable, but the pcb makers go into their
\"special\" options for that sort of thing.
Via in pad would need to be a micro via. The pad pitch is 0.5 mm and the width is 0.28 mm. I\'m not looking to make my life difficult. Some parts have 0.4 mm pad pitch.

One advantage of QFN is that there are no leads to get bent in production.

John

Bent leads basically don\'t happen with a decent surface-mount process,
even semi-auto or even manual. You just need the right equipment,
which is very modest for manual placement.

We just ordered a new Yamaha p+p machine. It looks cool in the Youtube
vids. Maybe they will throw in a piano or a motorcycle or something.

We\'ve had problems with CMs and QFNs, specifically solder dewetting.

With larger ones there are also potential board flex issues.

(We much prefer parts with leads.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[John Larkin]

On Mon, 24 Oct 2022 10:21:46 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

John Larkin wrote:
On Sun, 23 Oct 2022 03:46:00 -0700 (PDT), John Walliker
jrwalliker@gmail.com> wrote:

On Sunday, 23 October 2022 at 00:09:21 UTC+1, Ricky wrote:
On Saturday, October 22, 2022 at 3:41:35 PM UTC-4, Dimiter Popoff wrote:
On 10/22/2022 22:31, Ed Lee wrote:
On Saturday, October 22, 2022 at 12:27:08 PM UTC-7, Dimiter Popoff wrote:
On 10/22/2022 21:41, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

Depends on how many pins/pads are routed. Plugged vias on the signal pads are also possible.
Well he said it at the beginning, it is something like 3x4mm or was
it 4x5. Either way, a 0.2mm hole via with a 0.1mm annular ring is
small but how many can you fit under this. At 0.5mm pitch putting
such vias inside the signal pads is not doable even at 4 mil and
he is doing 6. I have not explored 0.1mm hole with 0.1mm annular
ring (i.e. 4 mil), looks doable, but the pcb makers go into their
\"special\" options for that sort of thing.
Via in pad would need to be a micro via. The pad pitch is 0.5 mm and the width is 0.28 mm. I\'m not looking to make my life difficult. Some parts have 0.4 mm pad pitch.

One advantage of QFN is that there are no leads to get bent in production.

John

Bent leads basically don\'t happen with a decent surface-mount process,
even semi-auto or even manual. You just need the right equipment,
which is very modest for manual placement.

We just ordered a new Yamaha p+p machine. It looks cool in the Youtube
vids. Maybe they will throw in a piano or a motorcycle or something.


We\'ve had problems with CMs and QFNs, specifically solder dewetting.

With larger ones there are also potential board flex issues.

(We much prefer parts with leads.)

Cheers

Phil Hobbs

I hate tiny leadless parts and hate them more of they have power pads.
They are nasty to rework or ECO and dangerous to probe.

No problem with bent leads. Solder joint inspection is expedited by
not being able to inspect them.

ST1L08SPUR would be the best LDO on the planet but it\'s in about the
worst imaginable package for an LDO. The best I can do is 25K/W. The
good news is that you can\'t get them.

 

[Ricky]

On Monday, October 24, 2022 at 10:21:58 AM UTC-4, Phil Hobbs wrote:

John Larkin wrote:
On Sun, 23 Oct 2022 03:46:00 -0700 (PDT), John Walliker
jrwal...@gmail.com> wrote:

On Sunday, 23 October 2022 at 00:09:21 UTC+1, Ricky wrote:
On Saturday, October 22, 2022 at 3:41:35 PM UTC-4, Dimiter Popoff wrote:
On 10/22/2022 22:31, Ed Lee wrote:
On Saturday, October 22, 2022 at 12:27:08 PM UTC-7, Dimiter Popoff wrote:
On 10/22/2022 21:41, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

Depends on how many pins/pads are routed. Plugged vias on the signal pads are also possible.
Well he said it at the beginning, it is something like 3x4mm or was
it 4x5. Either way, a 0.2mm hole via with a 0.1mm annular ring is
small but how many can you fit under this. At 0.5mm pitch putting
such vias inside the signal pads is not doable even at 4 mil and
he is doing 6. I have not explored 0.1mm hole with 0.1mm annular
ring (i.e. 4 mil), looks doable, but the pcb makers go into their
\"special\" options for that sort of thing.
Via in pad would need to be a micro via. The pad pitch is 0.5 mm and the width is 0.28 mm. I\'m not looking to make my life difficult. Some parts have 0.4 mm pad pitch.

One advantage of QFN is that there are no leads to get bent in production.

John

Bent leads basically don\'t happen with a decent surface-mount process,
even semi-auto or even manual. You just need the right equipment,
which is very modest for manual placement.

We just ordered a new Yamaha p+p machine. It looks cool in the Youtube
vids. Maybe they will throw in a piano or a motorcycle or something.

We\'ve had problems with CMs and QFNs, specifically solder dewetting.

With larger ones there are also potential board flex issues.

(We much prefer parts with leads.)

CMs being Contract Manufacturers? I\'m curious as to why you include them. Do you find CMs to be part of the problem? Do you do some of your own assembly which does not have a problem with QFNs?

--

Rick C.

--- Get 1,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209

 

[Phil Hobbs]

Ricky wrote:

On Monday, October 24, 2022 at 10:21:58 AM UTC-4, Phil Hobbs wrote:
John Larkin wrote:
On Sun, 23 Oct 2022 03:46:00 -0700 (PDT), John Walliker
jrwal...@gmail.com> wrote:

sniip
One advantage of QFN is that there are no leads to get bent in
production.

John

Bent leads basically don\'t happen with a decent surface-mount
process, even semi-auto or even manual. You just need the right
equipment, which is very modest for manual placement.

We just ordered a new Yamaha p+p machine. It looks cool in the
Youtube vids. Maybe they will throw in a piano or a motorcycle or
something.

We\'ve had problems with CMs and QFNs, specifically solder
dewetting.

With larger ones there are also potential board flex issues.

(We much prefer parts with leads.)

CMs being Contract Manufacturers? I\'m curious as to why you include
them. Do you find CMs to be part of the problem? Do you do some of
your own assembly which does not have a problem with QFNs?

I include them because that\'s where the problems have shown up.

We occasionally stuff boards ourselves, but not very often--since it\'s
gotten so cheap, we usually lay out a board and get the first run
fabbed and stuffed by JLCPCB. They\'re connected with LCSC, so most
parts are pretty cheap, and the ones that aren\'t, like the occasional
$10 op amp or $25 ADC, we stuff by hand as needed. Since a run of, say,
25 assembled boards is usually a few hundred bucks, it\'s no big
heartburn if they don\'t sell (or don\'t work, as sometimes happens).

BITD that would have been a much bigger hit.

Hand-stuffed boards have their issues, but with a decent inspection
microscope and a bit of healthy paranoia, dewets on QFNs aren\'t usually
among them.

Cheers

Phil Hobbs





--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Phil Hobbs]

Phil Hobbs wrote:

Ricky wrote:
On Monday, October 24, 2022 at 10:21:58 AM UTC-4, Phil Hobbs wrote:
John Larkin wrote:
On Sun, 23 Oct 2022 03:46:00 -0700 (PDT), John Walliker
jrwal...@gmail.com> wrote:

sniip
One advantage of QFN is that there are no leads to get bent in
production.

John

Bent leads basically don\'t happen with a decent surface-mount
process, even semi-auto or even manual. You just need the right
equipment, which is very modest for manual placement.

We just ordered a new Yamaha p+p machine. It looks cool in the
Youtube vids. Maybe they will throw in a piano or a motorcycle or
something.

We\'ve had problems with CMs and QFNs, specifically solder
dewetting.

With larger ones there are also potential board flex issues.

(We much prefer parts with leads.)

CMs being Contract Manufacturers?  I\'m curious as to why you include
them.  Do you find CMs to be part of the problem?  Do you do some of
your own assembly which does not have a problem with QFNs?

I include them because that\'s where the problems have shown up.

We occasionally stuff boards ourselves, but not very often--since it\'s
gotten so cheap, we usually lay out a board and get the first run fabbed
and stuffed by JLCPCB.  They\'re connected with LCSC, so most parts are
pretty cheap, and the ones that aren\'t, like the occasional $10 op amp
or $25 ADC, we stuff by hand as needed.  Since a run of, say, 25
assembled boards is usually a few hundred bucks, it\'s no big heartburn
if they don\'t sell (or don\'t work, as sometimes happens).

BITD that would have been a much bigger hit.

Hand-stuffed boards have their issues, but with a decent inspection
microscope and a bit of healthy paranoia, dewets on QFNs aren\'t usually
among them.

I should add that the QFN dewet problems we\'ve seen were more or less
equally distributed between the onshore and offshore vendors. \'T\'aint
just the Shenzhen folks, or even mostly.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[bitrex]

On 10/22/2022 2:01 PM, Ed Lee wrote:

On Saturday, October 22, 2022 at 10:59:37 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:22:41 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:20:42 AM UTC-7, John Larkin wrote:
On Sat, 22 Oct 2022 10:16:12 -0700 (PDT), Ed Lee
edward....@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?

How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
A pcb thermal pad smaller than the pad on the part invites shorts to
vias.
That\'s what blind vias are for.
LOL!

I guess it\'s regular vias with sunglasses (solder mask).

Us New England engineers don\'t wear shorts & sunglasses to work like
them California-types do.

 

[Ricky]

On Tuesday, October 25, 2022 at 10:32:33 PM UTC-4, Phil Hobbs wrote:

Ricky wrote:
On Monday, October 24, 2022 at 10:21:58 AM UTC-4, Phil Hobbs wrote:
John Larkin wrote:
On Sun, 23 Oct 2022 03:46:00 -0700 (PDT), John Walliker
jrwal...@gmail.com> wrote:

sniip
One advantage of QFN is that there are no leads to get bent in
production.

John

Bent leads basically don\'t happen with a decent surface-mount
process, even semi-auto or even manual. You just need the right
equipment, which is very modest for manual placement.

We just ordered a new Yamaha p+p machine. It looks cool in the
Youtube vids. Maybe they will throw in a piano or a motorcycle or
something.

We\'ve had problems with CMs and QFNs, specifically solder
dewetting.

With larger ones there are also potential board flex issues.

(We much prefer parts with leads.)

CMs being Contract Manufacturers? I\'m curious as to why you include
them. Do you find CMs to be part of the problem? Do you do some of
your own assembly which does not have a problem with QFNs?
I include them because that\'s where the problems have shown up.

We occasionally stuff boards ourselves, but not very often--since it\'s
gotten so cheap, we usually lay out a board and get the first run
fabbed and stuffed by JLCPCB. They\'re connected with LCSC, so most
parts are pretty cheap, and the ones that aren\'t, like the occasional
$10 op amp or $25 ADC, we stuff by hand as needed. Since a run of, say,
25 assembled boards is usually a few hundred bucks, it\'s no big
heartburn if they don\'t sell (or don\'t work, as sometimes happens).

BITD that would have been a much bigger hit.

Hand-stuffed boards have their issues, but with a decent inspection
microscope and a bit of healthy paranoia, dewets on QFNs aren\'t usually
among them.

Just so I understand, you seldom do any manufacturing other than using CMs, so there is nothing that indicates there\'s a connection between your CMs and problems with QFN assembly? Any problems you\'ve seen are just a function of the QFNs?

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209

 

[Phil Hobbs]

Ricky wrote:

On Tuesday, October 25, 2022 at 10:32:33 PM UTC-4, Phil Hobbs wrote:
Ricky wrote:
On Monday, October 24, 2022 at 10:21:58 AM UTC-4, Phil Hobbs
wrote:
John Larkin wrote:
On Sun, 23 Oct 2022 03:46:00 -0700 (PDT), John Walliker
jrwal...@gmail.com> wrote:

sniip
One advantage of QFN is that there are no leads to get bent
in production.

John

Bent leads basically don\'t happen with a decent
surface-mount process, even semi-auto or even manual. You
just need the right equipment, which is very modest for
manual placement.

We just ordered a new Yamaha p+p machine. It looks cool in
the Youtube vids. Maybe they will throw in a piano or a
motorcycle or something.

We\'ve had problems with CMs and QFNs, specifically solder
dewetting.

With larger ones there are also potential board flex issues.

(We much prefer parts with leads.)

CMs being Contract Manufacturers? I\'m curious as to why you
include them. Do you find CMs to be part of the problem? Do you
do some of your own assembly which does not have a problem with
QFNs?
I include them because that\'s where the problems have shown up.

We occasionally stuff boards ourselves, but not very often--since
it\'s gotten so cheap, we usually lay out a board and get the first
run fabbed and stuffed by JLCPCB. They\'re connected with LCSC, so
most parts are pretty cheap, and the ones that aren\'t, like the
occasional $10 op amp or $25 ADC, we stuff by hand as needed. Since
a run of, say, 25 assembled boards is usually a few hundred bucks,
it\'s no big heartburn if they don\'t sell (or don\'t work, as
sometimes happens).

BITD that would have been a much bigger hit.

Hand-stuffed boards have their issues, but with a decent
inspection microscope and a bit of healthy paranoia, dewets on QFNs
aren\'t usually among them.

Just so I understand, you seldom do any manufacturing other than
using CMs, so there is nothing that indicates there\'s a connection
between your CMs and problems with QFN assembly? Any problems you\'ve
seen are just a function of the QFNs?

We\'ve occasionally had other problems with CMs, of course, but no, apart
from first articles and rework we don\'t manufacture things here.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Ricky]

On Sunday, October 23, 2022 at 8:56:48 PM UTC-4, Dimiter Popoff wrote:

On 10/23/2022 18:06, John Larkin wrote:
On Sun, 23 Oct 2022 03:46:00 -0700 (PDT), John Walliker
jrwal...@gmail.com> wrote:

On Sunday, 23 October 2022 at 00:09:21 UTC+1, Ricky wrote:
On Saturday, October 22, 2022 at 3:41:35 PM UTC-4, Dimiter Popoff wrote:
On 10/22/2022 22:31, Ed Lee wrote:
On Saturday, October 22, 2022 at 12:27:08 PM UTC-7, Dimiter Popoff wrote:
On 10/22/2022 21:41, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

Depends on how many pins/pads are routed. Plugged vias on the signal pads are also possible.
Well he said it at the beginning, it is something like 3x4mm or was
it 4x5. Either way, a 0.2mm hole via with a 0.1mm annular ring is
small but how many can you fit under this. At 0.5mm pitch putting
such vias inside the signal pads is not doable even at 4 mil and
he is doing 6. I have not explored 0.1mm hole with 0.1mm annular
ring (i.e. 4 mil), looks doable, but the pcb makers go into their
\"special\" options for that sort of thing.
Via in pad would need to be a micro via. The pad pitch is 0.5 mm and the width is 0.28 mm. I\'m not looking to make my life difficult. Some parts have 0.4 mm pad pitch.

One advantage of QFN is that there are no leads to get bent in production.

John

Bent leads basically don\'t happen with a decent surface-mount process,
even semi-auto or even manual. You just need the right equipment,
which is very modest for manual placement.
I suppose qfn is about thermal contact with the PCB, too much of a pain
to use for no other good reason. We have used a tiny qfn MOSFET driver
for switchers, works fine and having just a few signals not a
pain to route. The Ethernet PHY we use in qfn OTOH has been a real pain
to deal with a few times when it needed rework. Out of the initial
good soldering it has been OK, just unnoticeable.

We just ordered a new Yamaha p+p machine. It looks cool in the Youtube
vids. Maybe they will throw in a piano or a motorcycle or something.

So your boards will be forming bands and motorcycle to gigs, not the
worst thing to happen .

I think thermal pads are about thermal issues, but QFNs are about making chips \"smaller\" even if they use as much or more real estate on the board. A lot of people don\'t look so hard at actual layout.

I don\'t recall people complaining about using them so much.

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209