QFN packages and layout on crowded PCBs...

[Ricky]

I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Ed Lee]

On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:

I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?

How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.

 

[John Larkin]

On Sat, 22 Oct 2022 10:16:12 -0700 (PDT), Ed Lee
<edward.ming.lee@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?

How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.

A pcb thermal pad smaller than the pad on the part invites shorts to
vias.

QFNs are hard to rework and hard to probe. Expect damage from probe
slips.

 

[Ricky]

On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:

On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.

I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand. But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[Ed Lee]

On Saturday, October 22, 2022 at 10:20:42 AM UTC-7, John Larkin wrote:

On Sat, 22 Oct 2022 10:16:12 -0700 (PDT), Ed Lee
edward....@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?

How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
A pcb thermal pad smaller than the pad on the part invites shorts to
vias.

That\'s what blind vias are for.

 

[Ed Lee]

On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:

On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.

Define a custom layout without thermal pad.

> But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.

Blind vias.

 

[Ed Lee]

On Saturday, October 22, 2022 at 10:25:21 AM UTC-7, Ed Lee wrote:

On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.

Actually, you don\'t care w/wo thermal pad for blind vias.

But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.

 

[Ed Lee]

On Saturday, October 22, 2022 at 10:30:43 AM UTC-7, Ed Lee wrote:

On Saturday, October 22, 2022 at 10:25:21 AM UTC-7, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package..

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.

Never mind. Ignore this:
> Actually, you don\'t care w/wo thermal pad for blind vias.
You do care.

 

[Ed Lee]

On Saturday, October 22, 2022 at 10:25:21 AM UTC-7, Ed Lee wrote:

On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.

Or externally insulated (painted) thermal pad.

 

[Ricky]

On Saturday, October 22, 2022 at 1:22:41 PM UTC-4, Ed Lee wrote:

On Saturday, October 22, 2022 at 10:20:42 AM UTC-7, John Larkin wrote:
On Sat, 22 Oct 2022 10:16:12 -0700 (PDT), Ed Lee
edward....@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?

How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
A pcb thermal pad smaller than the pad on the part invites shorts to
vias.
That\'s what blind vias are for.

LOL!

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[Ricky]

On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:

On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.

How can the via be blind when it needs to connect to the layer the pad is on???

The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[Ed Lee]

On Saturday, October 22, 2022 at 10:59:37 AM UTC-7, Ricky wrote:

On Saturday, October 22, 2022 at 1:22:41 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:20:42 AM UTC-7, John Larkin wrote:
On Sat, 22 Oct 2022 10:16:12 -0700 (PDT), Ed Lee
edward....@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?

How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
A pcb thermal pad smaller than the pad on the part invites shorts to
vias.
That\'s what blind vias are for.
LOL!

I guess it\'s regular vias with sunglasses (solder mask).

 

[Ed Lee]

On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:

On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package..

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???

\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.

> The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?

Haven\'t done it for some time.

 

[John Walliker]

On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:

On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.

Blind vias cost more.

John

 

[Ed Lee]

On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:

On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.

 

[Dimiter_Popoff]

On 10/22/2022 21:41, Ed Lee wrote:

On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.

At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

 

[John Larkin]

On Sat, 22 Oct 2022 10:22:38 -0700 (PDT), Ed Lee
<edward.ming.lee@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:20:42 AM UTC-7, John Larkin wrote:
On Sat, 22 Oct 2022 10:16:12 -0700 (PDT), Ed Lee
edward....@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?

How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
A pcb thermal pad smaller than the pad on the part invites shorts to
vias.

That\'s what blind vias are for.

We\'re designing a small, super dense board right now and blind+buried
vias were suggested. Sounds tricky to me. One problem is routing out
of a big Zynq 0.8 mm BGA. The cost of two more board layers is about a
wash with blind/buried.

You can\'t probe or hack a buried via.

But in this case, a surface pad still needs a surface via, and that
still collides with the power pad.

Tiny via-in-pad is a possibility for a QFN, but that could get nasty
too.

All these problems can be solved by applying money.

 

[Ed Lee]

On Saturday, October 22, 2022 at 12:27:08 PM UTC-7, Dimiter Popoff wrote:

On 10/22/2022 21:41, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.
At this size things get really different. The thermal pad he has is
not that big either so masking it won\'t buy him a lot.
The 6 mil he does is largish for parts like this, I do 4 mil with
0.2 holes, not that this would buy him a lot of area. 0.1 mm
holes are also an option but not within the typical \"standard\"
offerings. QFN has always been the worst package one has to deal
with for me, one just does what is possible and pray no rework is
ever needed.
I am so traumatized by the reworks I have had to do with a qfn
ethernet phy that recently I unsoldered and soldered it back countless
times and the green LED on the RJ45 just would not get on as
usual. Until I found out I had been plugging the wrong cable,
hanging empty at its other side....

Depends on how many pins/pads are routed. Plugged vias on the signal pads are also possible.

 

[John Larkin]

On Sat, 22 Oct 2022 11:41:38 -0700 (PDT), Ed Lee
<edward.ming.lee@gmail.com> wrote:

On Saturday, October 22, 2022 at 11:37:36 AM UTC-7, John Walliker wrote:
On Saturday, 22 October 2022 at 19:06:38 UTC+1, Ed Lee wrote:
On Saturday, October 22, 2022 at 11:01:08 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:25:21 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:21:15 AM UTC-7, Ricky wrote:
On Saturday, October 22, 2022 at 1:16:16 PM UTC-4, Ed Lee wrote:
On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?
How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
I don\'t define the size of the thermal pad. That\'s on the chip. I don\'t need to use the pad at all, from what I understand.
Define a custom layout without thermal pad.
But I would not want to run traces under the thermal pad on the package, even if the traces have solder mask. I certainly would not want to place vias under the thermal pad on the chip. That would result in shorts to the thermal pad on the chip which is typically grounded.
Blind vias.
How can the via be blind when it needs to connect to the layer the pad is on???
\"I guess it\'s regular vias with sunglasses (covered solder mask)\". Wrong term i supposed.
The problem is getting traces from this part, to the rest of the board. I take it, you don\'t do much layout yourself?
Haven\'t done it for some time.
Blind vias cost more.

Glue a thin plastic to the chip, or paint it. Very cheap.

That will be labor intensive and will lift the chip off the board,
with solderability issues.

 

[Ed Lee]

On Saturday, October 22, 2022 at 12:30:39 PM UTC-7, John Larkin wrote:

On Sat, 22 Oct 2022 10:22:38 -0700 (PDT), Ed Lee
edward....@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:20:42 AM UTC-7, John Larkin wrote:
On Sat, 22 Oct 2022 10:16:12 -0700 (PDT), Ed Lee
edward....@gmail.com> wrote:

On Saturday, October 22, 2022 at 10:12:02 AM UTC-7, Ricky wrote:
I\'ve been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.

A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.

An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.

Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.

Are there other reasons to use QFN packages for parts that don\'t have thermal issues? I\'ve never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?

How much power does the chip use? If you don\'t care about thermal, you can use a smaller pad and have room for via. Smaller thermal pad is better than none for secure mounting.
A pcb thermal pad smaller than the pad on the part invites shorts to
vias.

That\'s what blind vias are for.
We\'re designing a small, super dense board right now and blind+buried
vias were suggested. Sounds tricky to me. One problem is routing out
of a big Zynq 0.8 mm BGA. The cost of two more board layers is about a
wash with blind/buried.

You can\'t probe or hack a buried via.

But in this case, a surface pad still needs a surface via, and that
still collides with the power pad.

Tiny via-in-pad is a possibility for a QFN, but that could get nasty
too.

Plugged vias with high temperature solder.

> All these problems can be solved by applying money.

Money is no issue for some people.