Problem using $recordvars/$recordfile under NCverilog

Hi Danny:

I am also facing the same problem
Where do I find the missing library???
Do I need to contact Cadence.

-Navneet



danny_isr wrote:

> problem solved - missing library for NC.
 
"DW" <dave_wooff@hotmail.com> wrote in message
news:cas50f$nnn$1$830fa795@news.demon.co.uk...
Has anyone had any trouble using `include in Altera and/or Modelsim? I
have
a file in which a constant is `defined. The synthesizer will not accept
the
constant even though it does appear to be able to `include the file in
which
it is defined. I tried using a `define directly in the file but had the
same result.

What I want to do is to pass pipeline delay values back up the heirarchy
of
my design, such that the pipeline delay value at the top of the design is
automatically adjusted if I alter something at a lower level. I thought
about using `include files (one for each Verilog module) to communicate
this
information, but I had the problems mentioned above.

I then thought that perhaps I can use parameters as demonstrated below:

module1.v
=======
parameter module1_delay= n + module2_instance.module2_delay;

module2 module2_instance(...)

module2.v
=======
parameter module2_delay= m + module3_instance.module3_delay;

module3 module3_instance(...)

module3.v
=======
parameter module3_delay= p;

and so on. Is this a good idea?- it seems to be accepted by Quartus2 but
Modelsim complains that
"# ** Error: ../library/modulex.v(59): parameter value must be constant"

Has anyone any suggestions?

Thanks.
Click to expand...
Sorry everyone,
I found out that the accent ` is required on the definition wherever it is
used.
DW.
 
On 17 Jun 2004 10:59:34 -0700, Bassman59a@yahoo.com (Andy Peters)
wrote:

Figured I'd post this here, since I filed a defect report (DR
#00174902) in April and there's been no action.

Guess what very important feature Mentor Precision RTL synthesis does
NOT support -- but its predecessor, Leonardo, does?

You cannot override parameters from either the GUI or from a shell.

Believe it or not! A feature of Verilog that's been around, oh,
FOREVER! And, even worse is that they have no plans to address this
defect, as its status remains "assigned" and has not percolated up the
priority chain.

Point is: don't even bother considering this tool if you need to
parameterize your designs.
Click to expand...
Does it allow you to modify generics in VHDL (which are essentially
the same thing)?

Regards,
Allan.
 
Basically, you're not writing Verilog.
Very, very basic structures such as

if( condition ) begin [block of statements] end else begin [block of
statements] end

are necessary. I'd suggest learning a little more before trying to do a
conversion.
One suggestion for syntax related issues is to use a quick reference guide
such as that found at www.sutherland-hdl.com - check the "On-line Verilog
Ref" link toward the bottom of the list on the left.

Other statements like "assign" rather than
reg y; always@(x) case (x) 0: y=0; 1: y=1; default: y=0; endcase
you can use
wire y; assign y=x;
or even more simply if x is defined before wire y,
wire y = x;

Maybe a quick Verilog course is appropriate.


"Dave Wilson" <da_wils@hotmail.com> wrote in message
news:6895fdb2.0406180241.5bb1f918@posting.google.com...
Hello all,

I'm trying to convert some VHDL code to Verilog and have a few syntax
problems. Can anyone see what I'm doing wrong in this code ?

// 18-06-04

module sync_compare_verilog(clk,aclr,enable,out,get_ready_pulse
,main_sync,sync_polarity,missing_sync,sync_valid,sync_out);

input
clk,aclr,enable,get_ready_pulse,main_sync,sync_polarity,missing_sync;

output sync_valid,sync_out;

reg sync_valid;
reg sync_out;
reg state;

parameter zero=0, one=1;

always @(state)
begin
case (state)
zero:
out = 1'b0;
one:
out = 1'b1;
default:
out = 1'b0;
endcase
end

always @(posedge clk or posedge aclr)
begin
if (aclr)

sync_valid = 1'b0;
sync_out = 1'b0;
state = zero;
else
case (state)
zero: // ----------------------------- STATE 0

if (enable == 1'b1) // wait for enable
if (get_ready_pulse == 1'b1)
if (main_sync == 1'b1) and (sync_polarity = 1'b0) // check which
way ..
sync_valid = 1'b1;
// sync_out = main_sync; -- = 1
state = one;
else if (main_sync == 1'b0) and (sync_polarity == 1'b1)
sync_valid = 1'b1;
// sync_out = main_sync; -- = '0'
state = one;
else
sync_valid = 1'b0;
// sync_out = main_sync; -- = '0'
state = zero; // wait for the start conditions ..
end;
else
sync_valid = 1'b0;
//sync_out = main_sync; -- = '0'
state = zero; // wait for the start conditions ..
end;
else
state = zero;
end;

one: // ---------------------------------------- STATE 1

if (missing_sync == 1'b1)
sync_valid = 1'b0;
state = zero;
else
state = one;
//sync_out = main_sync;
end;
endcase
end;
endmodule
Click to expand...
 
"duststar" <g9102025@mail.ttu.edu.tw> Đ´ČëÓĘźţ
news:88809cfd.0406181417.250ca130@posting.google.com...
The XST User Guide says that it supports the indexed vector part
selects.
I tried to write a simple module as follows to test the part-select.
However, when i run synthesize in ISE 6.1i, the "ERROR:Xst:850 - ttt.v
line 14: Unsupported" message occured.
What's the problem? I have already updated my ise version to 6.1.03i.

////////////////////////////////////////////////////////////////
module ttt(clk, Din, Dout);
input clk;
input [127:0] Din;
output [127:0] Dout;
reg [127:0] Dout;
reg [7:0] temp [0:15];
integer i;
always@(posedge clk)
begin
for(i=0;i<=15;i=i+1)
begin
temp=Din[(127-8*i) -:8]; //line 14
~~What's this mean?
end
Dout={temp[0],temp[1],temp[2],temp[3],
temp[4],temp[5],temp[6],temp[7],
temp[8],temp[9],temp[10],temp[11],
temp[12],temp[13],temp[14],temp[15]};
end
endmodule
////////////////////////////////////////////////////////////////
Click to expand...
 
I just tried Xilinx Webpack(ISE) 6.2i (with SP3) -- same problem.
Apparently, XST (Xilinx Synthesis Technology) doesn't yet support
that Verilog-2001 syntax.

The XST Verilog preprocessor still doesn't support Macro-expressions,
either.

`define MAXIMUM2 ( x , y ) ( (x)>(y) ? (x) : (y) )

....

parameter COMMON_BUS_WIDTH = `MAXIMUM2( OUT_A, IN_B );

Steven Sharp wrote:
g9102025@mail.ttu.edu.tw (duststar) wrote in message news:<88809cfd.0406181417.250ca130@posting.google.com>...

The XST User Guide says that it supports the indexed vector part
selects.
I tried to write a simple module as follows to test the part-select.
However, when i run synthesize in ISE 6.1i, the "ERROR:Xst:850 - ttt.v
line 14: Unsupported" message occured.
What's the problem? I have already updated my ise version to 6.1.03i.


Your code works fine in NC-Verilog, so this must be an issue with XST.
Perhaps they require a command-line option to enable Verilog-2001
features. Or perhaps they support +: but not -:. Or perhaps they
don't like something about the expression you are using for the
starting bit position.
Click to expand...
 
On 18 Jun 2004 15:17:42 -0700, g9102025@mail.ttu.edu.tw (duststar)
wrote:

The XST User Guide says that it supports the indexed vector part
selects.
I tried to write a simple module as follows to test the part-select.
However, when i run synthesize in ISE 6.1i, the "ERROR:Xst:850 - ttt.v
line 14: Unsupported" message occured.
What's the problem? I have already updated my ise version to 6.1.03i.
Click to expand...
This bug was reported in comp.arch.fpga in January:
http://groups.google.com/groups?threadm=9phv00924evkervdfbj1bti6pf6cqdpsoe%404ax.com

BTW, they're up to 6.2.03i now. You are one release and three patches
behind.

Regards,
Allan.
 
On 20 Jun 2004 13:02:05 -0700, tom1@launchbird.com (Tom Hawkins)
wrote:

yxl4444@louisiana.edu (Lee) wrote in message news:<5c3c88bc.0406191558.3bf9eb50@posting.google.com>...
Dear all,

I have the following code,

module model_proto;
....
endmodule

module test;

model_proto inst 1
.
.
.
model_proto inst n

endmodele

Here, can I make n as flexible number (variable). When I call the
module in the other module, I can initialize n.

I need a module that have different number of instances. I don't like
to maintain two or more files. How can I make it?

In Verilog, you'll have to use generate/endgenerate, which can get messy.
Click to expand...

generate
genvar i;
for (i=1; i<=n; i=i+1) begin : must_have_label_here
model_proto inst ( ... );
end
endgenerate


I don't regard that as messy. I guess it's one of those "in the eye
of the beholder" things.


Regards,
Allan.
 
Heliboy wrote:

Folks,

I am trying to put the large Path Memory for Trace Back of Viterbi
Decoder in Block RAM of Xilinx Viterx FPGA. Say we have a 64 states,
trellis depth of 100 Trace Back and one decoded bit is output every
clock cycle. The problem is that how to store this path memory in
[...]
Click to expand...

http://www.obs-us.com/people/mihai/pdf/espld00.pdf

- try that document

If You'll have some problems ask again.

Jerzy Gbur
 
Think of using damem. It's a PLI we've used and it works kind of
reliably and does exactly what you want. Look for it on the web. You
should find it soon

-vs


Jim Wu wrote:

If you use VCS, it has a sparse memory model.

You may also want to take a look at TestBuilder which has support for
sparse memory model as well.

HTH,
Jim (jimwu88NOOOSPAM@yahoo.com remve NOOOSPAM)
http://www.geocities.com/jimwu88/chips


morteza wrote:

hello all

can anyone help me?

I want to model large memories in verilog.But you know that for
modeling for example 1M RAM memory about 32M in system is requierd.

so it will be fine if we could model the RAM elements in PLI.

can anyone help me for writing or finding such PLI?


with very best wishes
Click to expand...
 
well , our CAD guy solved it. i had to add this line to my .cshrc to make
it work. not sure if you missing the same library . hope it helps you.

setenv CDS_INST_DIR /tools/cadence/ldv_standard
 
Usually GPIO is just a data reg with a tristateable output. A corresponding
register controls the direction (in vs out) which same signal will also
tristate
the data register output. If the direction is out, a read at the data reg
location
will just give the data reg output contents. If direction reg is in, a read
of the
data reg will give the pin voltage.

reg [7:0] data_out, data_oen; // these are addressable
always @(posedge clk or negedge rstn)
if(~rstn) data <= 8'h0;
else if(write) data <= data;

wire [7:0] data_in;

assign data_in[7:0] = IOPIN[7:0];
assign IOPIN[7:0] = data_oen[7:0] ? data_out[7:0] : 8'hzz;

now when you decode on a read, read data_in.

BB

"Triste" <triste@myrealbox.com> wrote in message
news:6d3232ed.0407010816.9c5686f@posting.google.com...
Hi,

I'm a beginner in HDL. A GPIO specification is given requiring several
R/W registers driving and monitoring I/O pins on DigiLab board. I'm
not sure what R/W register is. Does it imply using
bi-directional/inout, or one input and one output?

Also, what does exactly GPIO do and what things I need to know before
designing the module.

Thanks very much,
triste
Click to expand...
 
You may try to do some manual floor planning then let the router do the
rest...

Don't expect the machine to understand everything you know...


Kelvin







"Heliboy" <heliboy2003@yahoo.com.tw> wrote in message
news:a91f428b.0407052243.69385c03@posting.google.com...
Folks,

I have this question for a long time, just could not get an answer.

Assume we have a design consisting of several blocks and some of those
blocks are hinhly regular (for example, a datapath). When we do P&R,
does the tool take the advantage of this regularity and place those
datapath element in series? Or it just does P&R globally without
looking at the local regularity?

The reason I am asking this is that we have a design with blocks which
are regular inside. But after P&R, the LUT utilization increases
dramatically, it seems it uses lots LUT for routing which isn't
expected just by looking at the regularity of the blocks.

Thanks.
Click to expand...
 
Hi,

If you don't want use two signal, you can think about tri-state signal
usage.
That doesn't give you a wait to informe other component; but if all
other block known that they must wait at least 4 clock cycle between
request and data disponibility, you are safe.

An other idea, it seems that you have the problem only at start, haven't
you ? Why don't include a top register to inhibate any communication
before 4 clock cycle after the reset ? In that wait, your ip can be well
initialize before any communication.

JaI

Lee wrote:

Hello,

I am writing verilog code for an IP core. In my current code, the
input is feed into at the first clock cycle. But the output can't be
ready at the first cycle and it will be ready at the fourth clock
cycle.

In the real chip, how to deal with this in order to cooperate with
other chip in the same PCB board?Give some output signals and they can
indicate when the output is ready?

Tell me the good way to solve this kind of problem,please.

Thanks,
Click to expand...
 
Hi Triste,

You have certainly some other features, but one of the first is
certainly a problem of clock race.
In case of cascaded divide-by-2, your output clock signal take each time
some little transmission delay; above a certain limit the output clock
is no more synchronized with input one.
With the single long divider (based on counter I think) you can reduce
this clock slide. And it is certainly more simple to resynchronize the
out clock.

JaI

Triste wrote:

Hi,

To derive a slow clock, say 1 Hz from 50 MHz or 32.768 KHz, does
anyone know the difference between using cascaded divide-by-2 counters
and using a single long divider?

Thanks very much in advance.
Click to expand...
 
Pablo Bleyer Kocik wrote:

Hello people.

I will be maintaining recent snapshots of the Icarus Verilog compiler
for the Windows platform in easy to use installers at
http://armoid.com/icarus/. I have been doing this for more than a year
now for the people in my company so I thought, what the heck, for the
same effort I can benefit other users out there.

If you have other free related goodies that can be posted there
--like Verilog test files, utility scripts, etc.-- please email me at
mailto:pbleyer2004N@SPAMembedded.cl [N@SPAM->@]

Thanks for Stephen Williams for putting together such a nice Verilog
compiler for the community.

Regards.

--
PabloBleyerKocik /"...I didn't want to be kissing Kevin Spacey.
pbleyer2004 / Come on! Lying there naked with rose petals?"
@embedded.cl /- Kirsten Dunst on turning down American Beauty
Click to expand...
How does the icarus compiler compare with the commercial ones, e.g.
modelsim, ncverilog, etc.?
 
Pablo Bleyer Kocik wrote:
Hello people.

I will be maintaining recent snapshots of the Icarus Verilog compiler
for the Windows platform in easy to use installers at
http://armoid.com/icarus/. I have been doing this for more than a year
now for the people in my company so I thought, what the heck, for the
same effort I can benefit other users out there.

If you have other free related goodies that can be posted there
--like Verilog test files, utility scripts, etc.-- please email me at
mailto:pbleyer2004N@SPAMembedded.cl [N@SPAM->@]

Thanks for Stephen Williams for putting together such a nice Verilog
compiler for the community.

Regards.
Click to expand...
I should add that Pablo has been sending me copies of his installer
that I keep in the "precompiled" directory where snapshots are
normally found. I should have a link to his site as well, unless
I forgot.

I still haven't booted Windows recently enough to try his installer
(lucky me!) so ride reports to comp.lang.verilog are welcome.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
 
In article <66691fdb.0407091415.2e7a1643@posting.google.com>, swang1
<swang@plxtech.com> writes
I want to write a waveform viewer, supporting VCD and EVCD. I have
VCD file format. Does anyone know where to get EVCD file format
definition ?
Click to expand...
Extended VCD format is created by ModelSim. In the ModelSim there is a
chapter on VCD and extended VCD file format. This is chapter 13 - Value
Change Dump (VCD) Files. One major difference between extended VCD and
VCD formats is that the port direction is implied by the state
character.
thanks
Click to expand...
Happy coding.
stephen
Click to expand...
--
Andy Botterill
 
--
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"." <nocker@animail.net> wrote in message
news:ab512dd8.0406190015.71bd12c2@posting.google.com...
comp.unix.cray,comp.windows.garnet,comp.os.ms-windows.programmer.winhelp,com
Click to expand...
p.os.ms-windows.networking.tcp-ip,comp.lang.verilog
 
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