PRC as a amplifier in GPS question.

Hell o ! Anyone out there? I think I'm a survivor.......now where's all the
aid going to come from ? France ? I don think so !!!

"chris" <ctg@bigpond.com> wrote in message
news:QsJId.130554$K7.93576@news-server.bigpond.net.au...
surfs up lol
well no matter even it it could reach me i have my car and dive gear so i
will just go for a drive lol
these political missguided knobs have no idea what they are on about lol
come to think of it no one else knows or cares



"Martin" <invalid.vk2umj@invalid.yahoo.com.au> wrote in message
news:34r4okF4djgdoU1@individual.net...
"Kevin Ettery" <kpettery@dcsi.net.au> wrote in message
news:41e7acf2@news.comindico.com.au...

tripe snipped

4) That whole population of NSW & Qld waiting like sitting duck, and
in
total ignorance of the terrible fate going to befall it! ... and that
Howard
Crew being warned of impeding disaster and NOT lifting his little
finger
to save millions of his own people ! A typical irresponsible,
careless
and in the circumstances Quite Criminal Attitude indeed ! Quite in
line
with the Port Arthur Holocaust Howard Government 's geared up &
further cover up following orchestrated by same !

more tripe snipped


Oh dear, another misguided soul that seems to think the entire
population
of
NSW & Qld lives on the coast. Hate ta break it to you mate but it'd
have
to
be a rather large tidal wave to put the whole population of these two
states
in peril - there's the little matter of the line of dirt called the
Great
Dividing Range that would break the back of your predicted tsunami.
Bring
on the quake & wave.

Ciao



Kevin

Hey, I might end up with an almost beach front house!!!!!
 
Yzordderrex wrote...
Winfield Hill wrote:
Hudson T. Clark wrote...

... I was also thinking about noise? Wouldn't it be catastrophic
if noise was present on the gates while switching several amperes?

With so much fierce stuff going on, be thankful that noise, in the
sense we normally think of it, isn't a factor. Consider a MOSFET
gate, with a typical gate capacitance of 2nF. Think of a typical
50MHz equivalent switching bandwidth. The impedance of 2nF at 50MHz
is under two ohms. As you know, low impedances like that won't be
sensitive to "noise" pickup, especially considering the high voltage
levels required to change the on/off state of a power MOSFET.

I have seen *If memory is correct* a 75kva full bridge converter
switching at 500kHz. It was a research project at UW-Madison 10
years ago. It was about the size of a toaster oven.
That's impressive. Usually such high-power units are made from many
paralleled lower-power modules. For 75kW use fifteen 5kW modules, or
ten 7.5kW modules, etc. Whether 5kW, 7.5kW, 15kW or whatever in each
module, that's a lot of power to run at 500kHz, so I'm impressed.

I am building a 1.5kw pep full bridge modulator that will fit into
a small cigar box.
I made a 500W 600kHz H-bridge with phase-shift controller, in about
half a cigar box. But it was painful to get at stuff, three layers,
etc., so when making a second one recently, I doubled the box size.


--
Thanks,
- Win
 
have you try to set focus after your repair?

Jim_Lazzaro@hotmail.com wrote:
Model ccd-tr75 Sony.
Have replaced all smd caps to make all camera functions work very well;
only the viewfinder appeared blurry.
So I proceeded to also change 4 mini caps on the viewfinder board and I
now have a blank screen (no video/image).
All circuit have been rechecked for shorts etc, and all is correct as
per schematics so my question is where could the problem be considering
this:
a)one cap (220uf 6.3v)was open/dried and I replaced with a 220uf/16v
b)one cap (82uf/10v)had high ESR and I replaced with whatever was
available being a 100uf/16v
Please, can anyone advise if changing these caps ( both marked SXE on
the schematis?) could have caused something to go bad? (my tests are
getting me nowhere and the only thing I notice is that the fbt area
gets quite hot)
Thank
Jim
 
Hey,
Could you please tell me more about setting the focus as this is my
first camcorder repair.
Much appreciated if you would.
Jim

klasspappa[remove] wrote:
have you try to set focus after your repair?

Jim_Lazzaro@hotmail.com wrote:
Model ccd-tr75 Sony.
Have replaced all smd caps to make all camera functions work very
well;
only the viewfinder appeared blurry.
So I proceeded to also change 4 mini caps on the viewfinder board
and I
now have a blank screen (no video/image).
All circuit have been rechecked for shorts etc, and all is correct
as
per schematics so my question is where could the problem be
considering
this:
a)one cap (220uf 6.3v)was open/dried and I replaced with a
220uf/16v
b)one cap (82uf/10v)had high ESR and I replaced with whatever was
available being a 100uf/16v
Please, can anyone advise if changing these caps ( both marked SXE
on
the schematis?) could have caused something to go bad? (my tests
are
getting me nowhere and the only thing I notice is that the fbt area
gets quite hot)
Thank
Jim
 
<Jim_Lazzaro@hotmail.com> wrote in message
news:1107265233.863876.93240@f14g2000cwb.googlegroups.com...
Thanks fellows, but .....:
I have just removed the 100 uf cap that I had replaced the original
with and put in the correct value being 82 uf (found at Speedy Spares
Melbourne). So the video came on good but I noticed a slight flickering
occasionally. Anyway about 5 minutes later all went blank, no picture
no light on crt of the virewfinder.
Tested things and found one shorted diode a one shorted transistor near
flyback.
How lucky can one get?
Can anyone please tell me why this happened? ( perhaps these components
were already going bad)
Jim
Quite easily the bad capacitor caused them to pop.
 
On Thu, 3 Feb 2005 04:26:11 +1100, <Nico> wrote:

Interfacing via ISA bus is very easy but slow and it is getting difficult to
find ISA based PCs.
This is the reason I keep ISA bus based PCs around and working.

USB bus easy to use but its packet stucture and therefore the latency is an
issue for some real-time applications.

So, I want to learn how to build and work/play with PCI interfaces. Can you
suggest what is the easiest and low-cost way of involving with the PCI bus
to learn with hands on experiments?
Well, ponying up to PCI will not be cheap. First, you need to understand the
difference between reflection wave and incident wave -- PCI is reflection wave.
Second, there are very tight constraints implied by the technology. Your PCI
clock line must be 1.5" +/- 0.1" in length, signal lines are to be less than
2.5" (if memory serves), and you will often find weird serpentine clock lines to
meet that 1.5" requirement. Third, because of the loading requirements (at
33MHz, some 10pF total; at 66Mhz, 5pF), you will be using an ASIC. No discrete
logic with multiple loads on single lines, for example. Fourth, you will pay
much more dearly for instruments that can monitor and display PCI bus signals.
Fifth, PCI mandates plug-and-play and certain minimum register requirements and
the ability to assign block addresses, if needed.

You can get low cost ASICs. But the rest makes this not low-cost and there is a
high threshold of knowledge required, as well. PCI was almost designed from the
ground up to exclude basement developers.

Jon
 
Jonathan Kirwan <jkirwan@easystreet.com> wrote:

On Thu, 3 Feb 2005 04:26:11 +1100, <Nico> wrote:

Interfacing via ISA bus is very easy but slow and it is getting difficult to
find ISA based PCs.

This is the reason I keep ISA bus based PCs around and working.

USB bus easy to use but its packet stucture and therefore the latency is an
issue for some real-time applications.

So, I want to learn how to build and work/play with PCI interfaces. Can you
suggest what is the easiest and low-cost way of involving with the PCI bus
to learn with hands on experiments?

Well, ponying up to PCI will not be cheap. First, you need to understand the
difference between reflection wave and incident wave -- PCI is reflection wave.
Second, there are very tight constraints implied by the technology. Your PCI
clock line must be 1.5" +/- 0.1" in length, signal lines are to be less than
2.5" (if memory serves), and you will often find weird serpentine clock lines to
Most modern PCB design packages will tell you the length of a trace.
No real problem here.

meet that 1.5" requirement. Third, because of the loading requirements (at
33MHz, some 10pF total; at 66Mhz, 5pF), you will be using an ASIC. No discrete
ASIC? FPGA will do just fine, but the chips made by PLX are often
found as a universal piece of glue.

logic with multiple loads on single lines, for example. Fourth, you will pay
much more dearly for instruments that can monitor and display PCI bus signals.
??? The 96 channel / 100MHz logic analyzer I picked up on Ebay for US$
66 works very nice to monitor PCI signals.

Fifth, PCI mandates plug-and-play and certain minimum register requirements and
the ability to assign block addresses, if needed.

You can get low cost ASICs. But the rest makes this not low-cost and there is a
high threshold of knowledge required, as well. PCI was almost designed from the
ground up to exclude basement developers.
Creating a PCI implementation is difficult, but there are numerous
ways to get a PCI core or bridge (like the PLX chips). No need to
bother with tedious timing.
The PCI specification can be downloaded from several sites. It just
comes down to a proper PCB layout on the PCI side.

The fastest way to get started with PCI is using a PLX chip.

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl
 
Jonathan Kirwan wrote:
On Wed, 02 Feb 2005 19:34:29 GMT, nico@puntnl.niks (Nico Coesel) wrote:


Creating a PCI implementation is difficult, but there are numerous
ways to get a PCI core or bridge (like the PLX chips). No need to
bother with tedious timing.
The PCI specification can be downloaded from several sites. It just
comes down to a proper PCB layout on the PCI side.

The fastest way to get started with PCI is using a PLX chip.


It's just not a hobbyist thing, frankly. The ISA is dirt easy and anyone can do
it.
Thanks for the hardware intro.
How about writing a driver ? There won't be single
stepping through code I'm afraid...

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
 
Jonathan Kirwan wrote:
On Wed, 02 Feb 2005 19:34:29 GMT, nico@puntnl.niks (Nico Coesel) wrote:


Creating a PCI implementation is difficult, but there are numerous
ways to get a PCI core or bridge (like the PLX chips). No need to
bother with tedious timing.
The PCI specification can be downloaded from several sites. It just
comes down to a proper PCB layout on the PCI side.

The fastest way to get started with PCI is using a PLX chip.


It's just not a hobbyist thing, frankly. The ISA is dirt easy and anyone can do
it.

Jon
AFAIK the PLX chips have a rather straight-forward backend bus, and I think some
of them can even do PCI to ISA if you really want to, so apart from the requirement that
you need to have a decent PCB if you want it to work reliably it shouldn't
be that difficult and PLX most likely have an app-note on how the PCB should look.

-Lasse
 
<Nico> wrote:

Interfacing via ISA bus is very easy but slow and it is getting difficult to
find ISA based PCs.
For the sake of argument... ISA boards are still very available in the
industrial market, and I think will be for many years. Cost is an issue
there, however. Since you are looking to learn, it is a good entry level
bus. Agreed, ISA is not exactly up to date technology.

USB bus easy to use but its packet stucture and therefore the latency is an
issue for some real-time applications.

So, I want to learn how to build and work/play with PCI interfaces. Can you
suggest what is the easiest and low-cost way of involving with the PCI bus
to learn with hands on experiments?
Nico, you didn't say what your price point is.

Someone else prove me wrong, but this is the lowest cost PCI proto board
I've seen. $150 USD. But wait -- there's more -- it includes USB, too.
It is CPLD based, so in theory you can use it for some other purposes
as well.... not as many options available as with a full FPGA, but a good
trade for the cost.

http://www.altera.com/products/devkits/altera/kit-maxii-1270.html

Thanks, Steve
 
On Wed, 02 Feb 2005 21:48:45 +0100, Rene Tschaggelar <none@none.net>
wrote:

Jonathan Kirwan wrote:
On Wed, 02 Feb 2005 19:34:29 GMT, nico@puntnl.niks (Nico Coesel) wrote:


Creating a PCI implementation is difficult, but there are numerous
ways to get a PCI core or bridge (like the PLX chips). No need to
bother with tedious timing.
The PCI specification can be downloaded from several sites. It just
comes down to a proper PCB layout on the PCI side.

The fastest way to get started with PCI is using a PLX chip.


It's just not a hobbyist thing, frankly. The ISA is dirt easy and anyone can do
it.

Thanks for the hardware intro.
How about writing a driver ? There won't be single
stepping through code I'm afraid...

We wrote a little DOS app that makes PCI bios calls. It can find a PCI
board and drag it down into a hole in the 640K-1M real address space
where you can bang the registers all you want. Works under DOS or
Win9x.

I wonder if there are any equivalent true-Windows programs.

John
 
Dave Rooney wrote:
Nico wrote:

Interfacing via ISA bus is very easy but slow and it is getting
difficult to find ISA based PCs.
USB bus easy to use but its packet stucture and therefore the latency
is an issue for some real-time applications.

So, I want to learn how to build and work/play with PCI interfaces.
Can you suggest what is the easiest and low-cost way of involving with
the PCI bus to learn with hands on experiments?




Try PLX Technology, www.plxtech.com. They make PCI bus interface chips
and they have eval boards and reference design kits for their parts.
I have used their parts on several projects and been very satisfied.

Dave Rooney
Thanks for the link. They also make some nice looking PCI Express bridge
and switch chips. Any experience with those Dave?

Geoff
 
On Wed, 02 Feb 2005 19:34:29 GMT, nico@puntnl.niks (Nico Coesel) wrote:


Creating a PCI implementation is difficult, but there are numerous
ways to get a PCI core or bridge (like the PLX chips). No need to
bother with tedious timing.
The PCI specification can be downloaded from several sites. It just
comes down to a proper PCB layout on the PCI side.

The fastest way to get started with PCI is using a PLX chip.


It's just not a hobbyist thing, frankly. The ISA is dirt easy and anyone
can do
it.

Thanks for the hardware intro.
How about writing a driver ? There won't be single
stepping through code I'm afraid...
You might want to take a look at this:

http://h-storm.tantos.homedns.org/hc_pci.htm

I've made this card exactly for this application: to allow myself to
interface to a modern PC without fighting with the PCI bus every time. It is
basically a simple ISA-like PCI bridge. You can attach a douther-card on top
of it and add whaterver circuit you like. You don't even need a driver if
you can go without interrupts.

Regards,
Andras Tantos
 
On Wed, 02 Feb 2005 23:40:56 +0000, Jonathan Kirwan wrote:

On Wed, 02 Feb 2005 23:43:25 +0100, Lasse Langwadt Christensen
langwadt@ieee.org> wrote:

AFAIK the PLX chips have a rather straight-forward backend bus, and I think some
of them can even do PCI to ISA if you really want to, so apart from the requirement that
you need to have a decent PCB if you want it to work reliably it shouldn't
be that difficult and PLX most likely have an app-note on how the PCB should look.

There is still a high learning curve if something does NOT work as you expect it
to. You need the tools and the knowledge.
It's not *that* difficult. The design kits have all the information
needed.

Of course, if everything works right out of the box, so to speak, then no
problem. But then reality does impinge.

I still do NOT consider PCI development to be hobbyist stuff.
It's certainly within the upper-end hobbyist's realm. ...at least with
the PLX bridge chips or prototype cards.

--
Keith
 
In article <c0m501t6gvk990vrer0tafivs9nhrmmnbc@4ax.com>,
jkirwan@easystreet.com says...
On 3 Feb 2005 15:12:33 -0800, aiiadict@gmail.com wrote:

Modern computer with PCI only, need to plug in an ISA card.

The southbridge or PCI-ISA bridge chip can only exist with "side-band" channels
to the main chipset.
No side-band channels/signals are needed.

There is only one of these possible, and then only if the
rest of the chipset supports the southbridge concept.
Only one "subtractive decoder" is possible. Southbridges use
"subtractive decoding", so only one southbridge is possible.

The side-band channels do
not exist as signals on the PCI bus, so I don't believe that it would be
possible to do a PCI board that provides full ISA -- more particularly, support
for ISA DMA.
Perhaps, but only because the DMA controller's addresses are already
used by the southbridge. ISA busmaster is also a likely "issue".

You might be able to get by with some specialized FPGA or ASIC for
the purposes of a reduced ISA feature set connecting to the PCI (no DMA and with
subtractive decoding for the ISA address space.)
The PLX 9052 is a PCI to ISA bridge. IIRC it's only a PCI target
device though.

--
Keith
 
Jonathan Kirwan <jkirwan@easystreet.com> wrote:

On 3 Feb 2005 15:12:33 -0800, aiiadict@gmail.com wrote:

Modern computer with PCI only, need to plug in an ISA card.

The southbridge or PCI-ISA bridge chip can only exist with "side-band" channels
to the main chipset. There is only one of these possible, and then only if the
rest of the chipset supports the southbridge concept. The side-band channels do
not exist as signals on the PCI bus, so I don't believe that it would be
possible to do a PCI board that provides full ISA -- more particularly, support
for ISA DMA. You might be able to get by with some specialized FPGA or ASIC for
the purposes of a reduced ISA feature set connecting to the PCI (no DMA and with
subtractive decoding for the ISA address space.)

I haven't heard of such a thing, though.
I think it is possible if the ISA card can use 1 interrupt or share
interrupts. You'll need some intelligence to convert ISA DMA to PCI
bus mastering (which is more or less the same, only the addresses are
generated at a different spot). The amount of I/O and memory addresses
can be preset on the PCI card so substractive addressing isn't needed.

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl
 
On Fri, 04 Feb 2005 16:25:30 GMT, nico@puntnl.niks (Nico Coesel) wrote:

I think it is possible if the ISA card can use 1 interrupt or share
interrupts. You'll need some intelligence to convert ISA DMA to PCI
bus mastering (which is more or less the same, only the addresses are
generated at a different spot).
The problem isn't that, it's the timing requirements of ISA DMA. They simply
cannot be met by the PCI bus using normal PCI transactions. This is part of why
the sideband signals are required to the main chipset, so that the chipset can
be informed about the non-standard nature of certain transactions. Without
them, the DMA timing itself cannot be supported on the PCI.

The amount of I/O and memory addresses
can be preset on the PCI card so substractive addressing isn't needed.
I suppose that's possible, of course. Usually, ISA bus transactions are handled
as subtractive decoding, though.

Jon
 
Jonathan Kirwan <jkirwan@easystreet.com> wrote:

On Fri, 04 Feb 2005 16:25:30 GMT, nico@puntnl.niks (Nico Coesel) wrote:

I think it is possible if the ISA card can use 1 interrupt or share
interrupts. You'll need some intelligence to convert ISA DMA to PCI
bus mastering (which is more or less the same, only the addresses are
generated at a different spot).

The problem isn't that, it's the timing requirements of ISA DMA. They simply
cannot be met by the PCI bus using normal PCI transactions. This is part of why
the sideband signals are required to the main chipset, so that the chipset can
be informed about the non-standard nature of certain transactions. Without
them, the DMA timing itself cannot be supported on the PCI.
I'm convinced it can be done with a trick: have the PCI-ISA bridge
read data from the ISA card first, store this and then send it to the
main memory. This way you separate the timing between the ISA and PCI
bus. This also allows for a smarter scheme in which more data is
buffered in the PCI bridge before it is send to the main memory.
You'll need to have the PCI bridge generate the addresses anyway.
Needless to say, you'll need to change the ISA driver software into a
PCI version as well.

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl
 
On Fri, 4 Feb 2005 15:20:35 -0500, Keith Williams <krw@att.bizzzz> wrote:

In article <ink701dhanogqu5kvljdad31qr36s2fil6@4ax.com>,
jkirwan@easystreet.com says...
On Fri, 4 Feb 2005 09:53:19 -0500, Keith Williams <krw@att.bizzzz> wrote:

The southbridge or PCI-ISA bridge chip can only exist with "side-band" channels
to the main chipset.

No side-band channels/signals are needed.

Why do you say this? It's certainly been true for as long as I've worked on
these chipsets. That does date back to the P2, but have things changed? I
doubt it.

No sideband signals are in the PCI spec (they wouldn't be
"sideband" ;-). Certainly the southbridge and subtractive decoding are
covered.
I was involved in chipset testing. One of the prominent examples where ISA
transactions simply cannot be translated to properly formed PCI transactions is
in the case of ISA DMA. There is no correct mapping possible -- the timing
requirements on the ISA side are "hard" and the PCI bus doesn't have the needed
transaction types to fully support ISA-side DMA without the sideband. So the
Intel chipsets all (up to the point where I stopped working with them directly,
anyway) included pins which were simply called "sideband." These pins couple
the southbridge with the main chipset in order to inform it about things like
ISA DMA, which have to be handled through PCI transactions but where the timing
requirements are hard and the chipset needs to support them. This was necessary
as PCI transactions had to be "twisted" a bit to make this work.

This is what I mean by sideband -- these out-of-band communications between the
southbridge and the main chipset for support of things like ISA DMA timing.

It was these sideband channels that accounted for about 1/2 of all chipset bugs,
so I know these sidebands exist. Plus, of course, I had to read the data sheets
and understand things like the inbound and outbound queuing, read around writes,
and a host of things regarding testing the chipsets with FPGA boards on both
sides of the southbridge, trying to break it.

Like I said, things may have changed. It's possible that I'd barely recognize
the PCI, today (though I doubt things have changed that much.) But I don't yet
see how ISA DMA timing, for one example, can be maintained exclusively through
standard PCI transactions and without any "extra communication" to the chipset.

I'm not saying that a reduced ISA wouldn't work -- it would. But there are a
few bits of non-overlapping semantics between ISA and PCI. And these are
usually handled by the sideband channel. I can assure you that if Intel could
have gotten rid of it, they would have clawed and screamed to do so. It was a
sink of engineering labor they would have been glad to be rid of.

Jon
 
"Jonathan Kirwan" <jkirwan@easystreet.com> wrote in message
news:hn280198c28c80j84pegpdt3q2jasjh4jk@4ax.com...
On Fri, 4 Feb 2005 15:20:35 -0500, Keith Williams <krw@att.bizzzz> wrote:

In article <ink701dhanogqu5kvljdad31qr36s2fil6@4ax.com>,
jkirwan@easystreet.com says...
On Fri, 4 Feb 2005 09:53:19 -0500, Keith Williams <krw@att.bizzzz
wrote:

The southbridge or PCI-ISA bridge chip can only exist with
"side-band" channels
to the main chipset.

No side-band channels/signals are needed.

Why do you say this? It's certainly been true for as long as I've
worked on
these chipsets. That does date back to the P2, but have things changed?
I
doubt it.

No sideband signals are in the PCI spec (they wouldn't be
"sideband" ;-). Certainly the southbridge and subtractive decoding are
covered.

I was involved in chipset testing. One of the prominent examples where
ISA
transactions simply cannot be translated to properly formed PCI
transactions is
in the case of ISA DMA. There is no correct mapping possible -- the
timing
requirements on the ISA side are "hard" and the PCI bus doesn't have the
needed
transaction types to fully support ISA-side DMA without the sideband. So
the
Intel chipsets all (up to the point where I stopped working with them
directly,
anyway) included pins which were simply called "sideband." These pins
couple
the southbridge with the main chipset in order to inform it about things
like
ISA DMA, which have to be handled through PCI transactions but where the
timing
requirements are hard and the chipset needs to support them. This was
necessary
as PCI transactions had to be "twisted" a bit to make this work.

This is what I mean by sideband -- these out-of-band communications
between the
southbridge and the main chipset for support of things like ISA DMA
timing.

It was these sideband channels that accounted for about 1/2 of all chipset
bugs,
so I know these sidebands exist. Plus, of course, I had to read the data
sheets
and understand things like the inbound and outbound queuing, read around
writes,
and a host of things regarding testing the chipsets with FPGA boards on
both
sides of the southbridge, trying to break it.

Like I said, things may have changed. It's possible that I'd barely
recognize
the PCI, today (though I doubt things have changed that much.) But I
don't yet
see how ISA DMA timing, for one example, can be maintained exclusively
through
standard PCI transactions and without any "extra communication" to the
chipset.

I'm not saying that a reduced ISA wouldn't work -- it would. But there
are a
few bits of non-overlapping semantics between ISA and PCI. And these are
usually handled by the sideband channel. I can assure you that if Intel
could
have gotten rid of it, they would have clawed and screamed to do so. It
was a
sink of engineering labor they would have been glad to be rid of.

Jon
The problem is a direct result of ordering rules. PCI (and basically all IO
buses) rely on certain ordering rules. Specific rules that apply in this
case are:

strong write ordering
- posted writes must arrive in order
- reads must flush writes (a read request must push posted writes ahead of
it (towards the target being read), and read completion (i.e. the read data)
must push posted writes ahead of it (toward the requestor of the read data)

deadlock avoidance
- writes must be able to pass requests (for example, read requests)

PCI has a retry mechanism for transactions and ISA does not. Once an ISA
device initiates a transaction there is no mechanism to get the master to
realease the bus until the transaction completes. The master can be held it
wait states, but you can't tell it to retry.

So, take the following scenario...

- the host has a posted write transaction heading towards the ISA bus (i.e.
it is temporarily stored in the chipset because the PCI bus was busy)

- the ISA bus is granted to a bus mastering device and the device intiates a
read of host memory

Without sideband signals, you have a deadlock condition. The read data being
returned the ISA bus master cannot be returned to the ISA bus before the
posted write that were buffered in the chipset. But, the posted write cannot
be delivered to the ISA bus because it is busy (the master is being held in
wait states waiting for the read data to be returned).

The sideband signals are used to make sure that the posted write buffers in
the chipset are flushed (empty) before an ISA bus master is granted the bus.

So, if you are implementing an ISA target device this isn't a problem (you
don't have an ISA bus master device).

These "sideband" signals are not documented in the PCI specifications. They
are chipset implementation specific signals and are private to the
motherboard.

TC



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