power supply dynamics...

[piglet]

On 01/07/2023 17:05, John Larkin wrote:

On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
jlarkin@highlandSNIPMEtechnology.com> wrote:


I want to build a cheap-ish 8-channel DC power supply.

Each channel can be a half-bridge, which is easy.

If I filter with an inductor and a low-ESR cap, I get good ripple but
if I take feedback from the output the loop dynamics, the phase
margin, sucks.

So why not take the voltage feedback from the switch node? No phase
lag! If we know the load current and the circuit losses, we can tweak
the output regulation pretty well.

https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl

The ADCs can even be synchronized to the PWM drive, so we can do FPGA
tricks to synchronously filter the maybe-ripply voltage feedback, or
just apply an arbitrarily complex lowpass filter ahead of the
closed-loop math.

Digitizing the current allows even fancier loop dynamics.


https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0

First pass at compound feedback. All the parts values are absolutely
first-guess as-drawn, and it\'s a tad underdamped. I\'m impressed that
it worked at all, first run.

The ringing is from the passive L1-C1 thing, not the loop. Some
damping could be added across C1 to kill the Q and beautify things
some. I might do that if there\'s room on the board.

Next step will be to hack in the real switching half-bridge and tune
things.

Sampling the switch node is giving you information about the supply
voltage and MOSFET Rdson. Voltage drop due to Rdson is probably going to
be much lower than inductor loss and inferable from current measurement.
For DC accuracy you most likely will still need to sample the post LC
output. For your AC dynamics you might as well just sample the raw
supply voltage?

piglet

 

[John Larkin]

On Mon, 3 Jul 2023 20:12:57 +0100, piglet <erichpwagner@hotmail.com>
wrote:

On 01/07/2023 17:05, John Larkin wrote:
On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
jlarkin@highlandSNIPMEtechnology.com> wrote:


I want to build a cheap-ish 8-channel DC power supply.

Each channel can be a half-bridge, which is easy.

If I filter with an inductor and a low-ESR cap, I get good ripple but
if I take feedback from the output the loop dynamics, the phase
margin, sucks.

So why not take the voltage feedback from the switch node? No phase
lag! If we know the load current and the circuit losses, we can tweak
the output regulation pretty well.

https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl

The ADCs can even be synchronized to the PWM drive, so we can do FPGA
tricks to synchronously filter the maybe-ripply voltage feedback, or
just apply an arbitrarily complex lowpass filter ahead of the
closed-loop math.

Digitizing the current allows even fancier loop dynamics.


https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0

First pass at compound feedback. All the parts values are absolutely
first-guess as-drawn, and it\'s a tad underdamped. I\'m impressed that
it worked at all, first run.

The ringing is from the passive L1-C1 thing, not the loop. Some
damping could be added across C1 to kill the Q and beautify things
some. I might do that if there\'s room on the board.

Next step will be to hack in the real switching half-bridge and tune
things.



Sampling the switch node is giving you information about the supply
voltage and MOSFET Rdson. Voltage drop due to Rdson is probably going to
be much lower than inductor loss and inferable from current measurement.
For DC accuracy you most likely will still need to sample the post LC
output. For your AC dynamics you might as well just sample the raw
supply voltage?

piglet

Here is is:

https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1

The loop feedback is a mixture of the raw switching from the
half-bridge, and the actual DC output. Dynamics look great. The two
bumps are from a pulsed load.

One nice thing, in a power supply, is that it behaves pretty well no
matter what crazy things the customer may connect it to.

Many power supplies try to solve that problem by having huge output
caps, which make giant sparks when the supply is shorted, no matter
what the current limit is set to. I won\'t have room for giant caps
anyhow.

That LTC driver is supposed to have shoot-thru protection, but the top
fet was frying in simulation. We\'ll actually use the TI driver, and
our FPGA can add shoot-thru timing if we need it. The actual control
loop will be all digital.

One sim run like in the pic takes maybe 20 minutes. I had lunch and
hosed out the garage during runs. Maybe I need a new PC.

It\'s hard to tune a control loop with 20 minute feedback.

 

[Erich Wagner]

On Monday, 3 July 2023 at 22:02:53 UTC+1, John Larkin wrote:

On Mon, 3 Jul 2023 20:12:57 +0100, piglet <erichp...@hotmail.com
wrote:
On 01/07/2023 17:05, John Larkin wrote:
On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
jla...@highlandSNIPMEtechnology.com> wrote:


I want to build a cheap-ish 8-channel DC power supply.

Each channel can be a half-bridge, which is easy.

If I filter with an inductor and a low-ESR cap, I get good ripple but
if I take feedback from the output the loop dynamics, the phase
margin, sucks.

So why not take the voltage feedback from the switch node? No phase
lag! If we know the load current and the circuit losses, we can tweak
the output regulation pretty well.

https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl

The ADCs can even be synchronized to the PWM drive, so we can do FPGA
tricks to synchronously filter the maybe-ripply voltage feedback, or
just apply an arbitrarily complex lowpass filter ahead of the
closed-loop math.

Digitizing the current allows even fancier loop dynamics.


https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0

First pass at compound feedback. All the parts values are absolutely
first-guess as-drawn, and it\'s a tad underdamped. I\'m impressed that
it worked at all, first run.

The ringing is from the passive L1-C1 thing, not the loop. Some
damping could be added across C1 to kill the Q and beautify things
some. I might do that if there\'s room on the board.

Next step will be to hack in the real switching half-bridge and tune
things.



Sampling the switch node is giving you information about the supply
voltage and MOSFET Rdson. Voltage drop due to Rdson is probably going to
be much lower than inductor loss and inferable from current measurement.
For DC accuracy you most likely will still need to sample the post LC
output. For your AC dynamics you might as well just sample the raw
supply voltage?

piglet

Here is is:

https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1

The loop feedback is a mixture of the raw switching from the
half-bridge, and the actual DC output. Dynamics look great. The two
bumps are from a pulsed load.

One nice thing, in a power supply, is that it behaves pretty well no
matter what crazy things the customer may connect it to.

Many power supplies try to solve that problem by having huge output
caps, which make giant sparks when the supply is shorted, no matter
what the current limit is set to. I won\'t have room for giant caps
anyhow.

That LTC driver is supposed to have shoot-thru protection, but the top
fet was frying in simulation. We\'ll actually use the TI driver, and
our FPGA can add shoot-thru timing if we need it. The actual control
loop will be all digital.

One sim run like in the pic takes maybe 20 minutes. I had lunch and
hosed out the garage during runs. Maybe I need a new PC.

It\'s hard to tune a control loop with 20 minute feedback.

What is the 48v supply impedance, can’t see the series resistance of v6?
piglet

 

[John Larkin]

On Tue, 4 Jul 2023 04:17:47 -0700 (PDT), Erich Wagner
<erichpwagner@hotmail.com> wrote:

On Monday, 3 July 2023 at 22:02:53 UTC+1, John Larkin wrote:
On Mon, 3 Jul 2023 20:12:57 +0100, piglet <erichp...@hotmail.com
wrote:
On 01/07/2023 17:05, John Larkin wrote:
On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
jla...@highlandSNIPMEtechnology.com> wrote:


I want to build a cheap-ish 8-channel DC power supply.

Each channel can be a half-bridge, which is easy.

If I filter with an inductor and a low-ESR cap, I get good ripple but
if I take feedback from the output the loop dynamics, the phase
margin, sucks.

So why not take the voltage feedback from the switch node? No phase
lag! If we know the load current and the circuit losses, we can tweak
the output regulation pretty well.

https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl

The ADCs can even be synchronized to the PWM drive, so we can do FPGA
tricks to synchronously filter the maybe-ripply voltage feedback, or
just apply an arbitrarily complex lowpass filter ahead of the
closed-loop math.

Digitizing the current allows even fancier loop dynamics.


https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0

First pass at compound feedback. All the parts values are absolutely
first-guess as-drawn, and it\'s a tad underdamped. I\'m impressed that
it worked at all, first run.

The ringing is from the passive L1-C1 thing, not the loop. Some
damping could be added across C1 to kill the Q and beautify things
some. I might do that if there\'s room on the board.

Next step will be to hack in the real switching half-bridge and tune
things.



Sampling the switch node is giving you information about the supply
voltage and MOSFET Rdson. Voltage drop due to Rdson is probably going to
be much lower than inductor loss and inferable from current measurement.
For DC accuracy you most likely will still need to sample the post LC
output. For your AC dynamics you might as well just sample the raw
supply voltage?

piglet

Here is is:

https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1

The loop feedback is a mixture of the raw switching from the
half-bridge, and the actual DC output. Dynamics look great. The two
bumps are from a pulsed load.

One nice thing, in a power supply, is that it behaves pretty well no
matter what crazy things the customer may connect it to.

Many power supplies try to solve that problem by having huge output
caps, which make giant sparks when the supply is shorted, no matter
what the current limit is set to. I won\'t have room for giant caps
anyhow.

That LTC driver is supposed to have shoot-thru protection, but the top
fet was frying in simulation. We\'ll actually use the TI driver, and
our FPGA can add shoot-thru timing if we need it. The actual control
loop will be all digital.

One sim run like in the pic takes maybe 20 minutes. I had lunch and
hosed out the garage during runs. Maybe I need a new PC.

It\'s hard to tune a control loop with 20 minute feedback.

What is the 48v supply impedance, can’t see the series resistance of v6?
piglet

The 48 supply is a kilowatt MeanWell switcher, and I\'m assuming it\'s a
perfect voltage source. These will be relatively tiny supplies,
ballpark 20 watts each maybe, so they shouldn\'t affect the 48v buss
much.

And, as I tell people, it\'s just a power supply.

I actually see people putting bypass caps across voltage sources in
Spice! It\'s sometimes hard to remember that we\'re simulating, that
dissipating 20 watts in a pullup resistor doesn\'t matter, or that 50
ohm resistors are actually 49.9.

Well, sometimes we add stuff that\'s not sensible in simulation, as
reminders about real life later. Like the gate resistors.

 

[tridac]

On 6/30/23 22:39, John Larkin wrote:

On Fri, 30 Jun 2023 16:09:11 -0400, bitrex <user@example.net> wrote:

On 6/30/2023 1:39 PM, John Larkin wrote:

I want to build a cheap-ish 8-channel DC power supply.

Each channel can be a half-bridge, which is easy.

If I filter with an inductor and a low-ESR cap, I get good ripple but
if I take feedback from the output the loop dynamics, the phase
margin, sucks.

So why not take the voltage feedback from the switch node? No phase
lag! If we know the load current and the circuit losses, we can tweak
the output regulation pretty well.

https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl

The ADCs can even be synchronized to the PWM drive, so we can do FPGA
tricks to synchronously filter the maybe-ripply voltage feedback, or
just apply an arbitrarily complex lowpass filter ahead of the
closed-loop math.

Digitizing the current allows even fancier loop dynamics.

Why not Sense the output voltage with a separate diode and smaller cap
just to sense the voltage alone ?. Depends on what regulation you need.
but why add complexity and cost with an fpga. Overthinking ?

Chris

Since you\'re using a FPGA anyway do you even need to low-pass the switch
node voltage in analog and send it to an ADC first?

Just to take out any really fast spikes.



Since you\'re pre-filter anyway I think you could just level-shift and
send the bit streams on the gates of Q1 and Q2 to pins on the FPGA, as
your \"1 bit ADCs\" if you will


The FPGA is driving the fets, so we know their state. The +48 could
wander a bit, and it doesn\'t know that.

 

[John Larkin]

On Tue, 4 Jul 2023 23:34:28 +0000, tridac <syseng@gfsys.co.uk> wrote:

On 6/30/23 22:39, John Larkin wrote:
On Fri, 30 Jun 2023 16:09:11 -0400, bitrex <user@example.net> wrote:

On 6/30/2023 1:39 PM, John Larkin wrote:

I want to build a cheap-ish 8-channel DC power supply.

Each channel can be a half-bridge, which is easy.

If I filter with an inductor and a low-ESR cap, I get good ripple but
if I take feedback from the output the loop dynamics, the phase
margin, sucks.

So why not take the voltage feedback from the switch node? No phase
lag! If we know the load current and the circuit losses, we can tweak
the output regulation pretty well.

https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl

The ADCs can even be synchronized to the PWM drive, so we can do FPGA
tricks to synchronously filter the maybe-ripply voltage feedback, or
just apply an arbitrarily complex lowpass filter ahead of the
closed-loop math.

Digitizing the current allows even fancier loop dynamics.


Why not Sense the output voltage with a separate diode and smaller cap
just to sense the voltage alone ?. Depends on what regulation you need.
but why add complexity and cost with an fpga. Overthinking ?

Chris

I posted the almost-final circuit below, repeated here

https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1

It does combine fast feedback from the switch node and slow feedback
from the final output. That gives good dynamics and good regulation.

The board plugs into a mainframe and needs the FPGA to handshake with
the main controller, a MicroZed board. The FPGA allows a lot of
features too, like programmable slew rate, cc/cv/cr modes, data
logging, things like that. The Efinix part is just $10.