Power-On Reset

[Ken Smith]

In article <bm5n11tgkqmivr729e86r7anbjmg4oak32@4ax.com>,
Jim Thompson <thegreatone@example.com> wrote:
[...]

So a smart-aleck came along and did a machine-gun staccato with the
ON/OFF switch, and flame erupted ;-)

I had the same problem without the smart-aleck. It was a bad contact in a
customer supplied winch slip-ring assembly. It went open-connect-open at
maybe 10Hz. I had to add a circuit that turned the power off if the
current stopped.


--
--
kensmith@rahul.net forging knowledge

 

[Ken Smith]

In article <pan.2005.02.22.19.43.32.464662@example.net>,
Rich Grise <richgrise@example.net> wrote:
[...]

I wondered, "WTF MEMS???" so I looked it up.

Sh*t man f*ck - it ain't that far from reality! Nanomachines! Buckytubes!
The one-atom motor!

Or is that a whole nother level of reality?

We already have the electron-proton based M-G set so we have already
passed the one atom point. Hint: Overhauser

--
--
kensmith@rahul.net forging knowledge

 

[Allan Herriman]

On Tue, 22 Feb 2005 23:03:31 +0000, Guy Macon
<http://www.guymacon.com/> wrote:

(Why did you crosspostthis to sci.electronics.cad? There is a
reason why different newsgroups have different names; it is so
that someone interested in electronics CAD does not have to wade
through off-topic posts about electronics design.)

For the simple reason that it was replying to something that had been
posted to sci.electronics.cad.
Perhaps your comments should be directed to the OP (?)

Regards,
Allan

 

[Paul Burke]

Guy Macon wrote:

The fact that Intel provided the function on an external chip says
something, I'm not sure what, about doing it inside the micro.
It says that at some time in the past it was easier to design a
dedicated chip that behaves correctly at all voltages, and it was
easier to design a microprocessor that expects a reset after the
power supply becomes stable.

If you want an example of someoone trying to get it von-chip, and the
problems that resulted, look up the MSP430's brownout feature. It
remains one of the poorer aspects of the design, and you still need an
external reset if you really want it to be reliable. Which is a bugger,
as this can consume as much current as the rest of the circuit put together.

Paul Burke

 

[Ken Smith]

In article <bfco11dv6vasme5v2nro90l22ja5u3el14@4ax.com>,
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

On Tue, 22 Feb 2005 19:29:16 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) wrote:
[...]
Many FPGA and CPLD circuits do not become sane until the supply voltage
[...]
I fixed it by gating the port outputs with a 74HC part.

Unfortunately I just caught a part holding its output high until Vcc was
high enough to be taken as logic high by a 74HC part. I've had to add and
and gate to the system.

--
--
kensmith@rahul.net forging knowledge

 

[Guy Macon]

Allan Herriman wrote:

Guy Maco wrote:

(Why did you crosspostthis to sci.electronics.cad? There is a
reason why different newsgroups have different names; it is so
that someone interested in electronics CAD does not have to wade
through off-topic posts about electronics design.)

For the simple reason that it was replying to something that had been
posted to sci.electronics.cad.

Posting to inappropriate newsgroups because that's where the
post you replied to happened to be is like shitting in your
pants because that's where your ass happened to be.

 

[keith]

On Wed, 23 Feb 2005 07:42:34 -0700, Jim Thompson wrote:

On Wed, 23 Feb 2005 18:25:34 +1100, Allan Herriman
allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

On Tue, 22 Feb 2005 23:03:31 +0000, Guy Macon
http://www.guymacon.com/> wrote:

(Why did you crosspostthis to sci.electronics.cad? There is a
reason why different newsgroups have different names; it is so
that someone interested in electronics CAD does not have to wade
through off-topic posts about electronics design.)

For the simple reason that it was replying to something that had been
posted to sci.electronics.cad.
Perhaps your comments should be directed to the OP (?)

Regards,
Allan

I figured to find more ASIC designers on sci.electronics.cad than on
S.E.D, only "flashers" hang out there ;-)

I'll show you mine if you show me yours! ;-)


--
Keith

 

[keith]

On Wed, 23 Feb 2005 18:27:01 +1100, Allan Herriman wrote:

On Tue, 22 Feb 2005 19:35:04 GMT, Rich Grise <richgrise@example.net
wrote:

On Tue, 22 Feb 2005 15:20:51 +0000, Michael A. Terrell wrote:
Rich Grise wrote:
On Tue, 22 Feb 2005 04:10:28 +0000, Paul Rako wrote:
...
over a range of temperatures and loads. This is really a
design challenge so don't take it lightly.

What's wrong with a 1 uF cap from the POR pin to ground, with,
say, a 10K pullup?

Thanks,
Rich

If you ever had to troubleshoot equipment built that way you would
never ask that question. The VTR interfaces for a video editing system
at WACX in Orlando was designed for a reset generator chip, then they
left out the chip and used a crappy R/C reset. The equipment worked
when it was new but a couple years later it would only reset one out of
20 or more attempts. You could play around with the R/C values and make
it work for a couple weeks, but they finally agreed to let me mod the
equipment by stuffing the missing parts on the board and eliminated the
problems.

But notice the operative phrase here - "designed for a reset generator
chip". That particular chip does, in fact, need a proper reset, as has
been covered in other posts in the thread.

I was talking about the kinds of chips that they made in the '80s, where
there was a pin specifically designed to take a cap and R, and has a
Schmitt trigger, and the whole chip is designed to get reset by that
little circuit.

These were never reliable. Even in the '80s.

They are/were quite reliable if you know the power supply properties
(or get to specify them). I've had many desings in places that the power
supply sequencing, timing and slew was very tightly controlled (usually
for other reasons). In controlled environments a fancy POR circuit is
overkill and perhaps not possible.

--
Keith

 

[Allan Herriman]

On Tue, 22 Feb 2005 10:40:56 GMT, Rich Grise <richgrise@example.net>
wrote:

On Tue, 22 Feb 2005 04:10:28 +0000, Paul Rako wrote:

POR circuits are NOT trivial to design. Many people
have crashed and burned using latches, 555 timers and
other schemes. This is why Maxim can get 50 cents for
a reset chip. I have been told by very smart people that
the only valid approach to a POR circuit is a transistor-
level approach. You have to have fully characterized
transistor models if you expect to SPICE it, macromodels
will not do. Be sure to exercise the circuit (reality preferred
to SPICE) for very slow as well as very fast power turn-on and
over a range of temperatures and loads. This is really a
design challenge so don't take it lightly.


What's wrong with a 1 uF cap from the POR pin to ground, with,
say, a 10K pullup?

Rich, I am unable to tell whether you were being sarcastic, or whether
you really don't know why an RC circuit is a bad reset generator (in
general).


Commonly encountered supply waveforms that don't produce a reliable
reset from the RC circuit:

1. A brief dip in the supply voltage that goes low enough to crash
the processor, but it doesn't discharge the cap enough to cause a
reset when the supply returns to normal.

2. Very slow dv/dt. The RC circuit will not assert reset.

3. The supply voltage sitting in a "brownout" state indefinitely.
The RC circuit will not assert reset.


A good reset generator will hold reset active for all values of supply
voltage below some threshold all the way down to zero volts,
regardless of dv/dt (except maybe for glitch filtering), and keep
reset active for a certain period (some tens to hundreds of ms) after
the voltage goes above the threshold.


Regards,
Allan

 

[Jim Thompson]

On Tue, 22 Feb 2005 16:57:16 GMT, Paul Rako
<s_p_ortsterpa_u_l@yahoo.com> wrote:

[snip]

If JT has a circuit that he can vary process corners it looks like he
understands the grief of doing a POR.

I've been thru MUCH grief in my design lifetime, that's why I'm
cautious as hell.

I have worked with a lot of
digital guys that just can't comprehend that gate-level SPICE just
does not work when the rails are at 1.7 volts.

Digital guys are amusing, aren't they ?

Heck, Bob Pease would
say that analog SPICE doesn't work much better (;^o)-

I think Bob is becoming over-exaggerative in his old age. Picks
absurd examples. Must be running out of material for his column.

(Of course I'm a young man compared to Bob. He graduated MIT in 1961,
I graduated MIT in 1962

Hot-swap circuits are equally non-trivial. Did the card get stuck
in for a millisecond, then yanked out, then stuck back in-- what is
the state of all the circuits on both the mother and daughtercard..
ect ect ect

Paul

[snip]

My application isn't hot-swap, but it's similar... even has a
charge-pump, which turned out to be helpful in making the POR timing
;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Rich Grise]

On Tue, 22 Feb 2005 08:44:20 -0700, Jim Thompson wrote:

On Tue, 22 Feb 2005 15:31:52 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) wrote:

In article <t9jm11p41336lqrgp8n8g7g5qatrkas8fs@4ax.com>,
Jim Thompson <thegreatone@example.com> wrote:
[...]
I've found a solution I can't divulge at the moment, maybe in two
years, that tracks process corners and times relative to what needs
the reset.

Add a clock monitor input so that you are sure that the system clock is
running before you drop the reset.

I assume you are using a MEMS relay and dashpot so adding a stepper relay
shouldn't be too hard.

--

ROTFLMAO ;-)

I wondered, "WTF MEMS???" so I looked it up.

Sh*t man f*ck - it ain't that far from reality! Nanomachines! Buckytubes!
The one-atom motor!

Or is that a whole nother level of reality?

Thanks,
Rich