Power-On Reset

[Jim Thompson]

I need a power-on reset that lasts around 5ms.

Process is CMOS

1.65V < VDD < 5.5V

Components available besides CMOS:

Lateral PNP
Vertical PNP
Caps up to 20pF
Resistors up to 1Meg

Suggestions?

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Tim Shoppa]

Suggestions?

Many of the recent Microchip PIC power-on-resets use a digital counter
internally. I'm guessing that they're working within confines similar
to what you have and also they're trying to keep power consumption
while asleep to a minimum and deal with brownout recovery. I don't
know the details but they must be taking on-chip clock in the 10's or
100's of kHz to tick everything along.

What requirements do you have regarding power consumption while asleep,
brownout recovery, ?

Tim.

 

[Harry Dellamano]

"Jim Thompson" <thegreatone@example.com> wrote in message
news:9rak019gmhk7bu03ksmmb4bcgq9anmhf92@4ax.com...

I need a power-on reset that lasts around 5ms.

Process is CMOS

1.65V < VDD < 5.5V

Components available besides CMOS:

Lateral PNP
Vertical PNP
Caps up to 20pF
Resistors up to 1Meg

Suggestions?

Your favorite oscillator and a 20 bit counter. In the meantime you can

continue work on that cap multiplier.
Cheers,
Harry

 

[John Larkin]

On Wed, 09 Feb 2005 08:31:23 -0700, Jim Thompson
<thegreatone@example.com> wrote:

I need a power-on reset that lasts around 5ms.

Process is CMOS

1.65V < VDD < 5.5V

Components available besides CMOS:

Lateral PNP
Vertical PNP
Caps up to 20pF
Resistors up to 1Meg

Suggestions?

...Jim Thompson

Why not just hold reset true as long as Vcc is below some level?

John

 

[Tony Williams]

In article <9rak019gmhk7bu03ksmmb4bcgq9anmhf92@4ax.com>,
Jim Thompson <thegreatone@example.com> wrote:

I need a power-on reset that lasts around 5ms.
Process is CMOS
1.65V < VDD < 5.5V
Components available besides CMOS:
Lateral PNP
Vertical PNP
Caps up to 20pF
Resistors up to 1Meg

50KHz relaxation osc, 8 bit counter, flip flop?

There was an experimental thread here last year on
CMOS flip flops that indicated that they could be
'guided' into the required POR state by pull up/down
R's. That could maybe be the way to bring up the counter
and flip flop in the Reset state.

--
Tony Williams.

 

Similar non-stand-alone functions that people have
designed into chips
tend to be inferior to parts
such as the above.

I think that battery-operated consumer single-chip gizmos were using a
similar (although probably no band-gap) technique back into the early
80's. At least that was the only way I could figure they were
generating a power-on-reset delay of hundreds of ms. Some of these
worked down below 1.2V. I never did figure out what magic they used
internally (maybe related to, or even exactly the same as, Jim's
mention of an internal charge pump?)

Tim.

 

Similar non-stand-alone functions that people have
designed into chips
tend to be inferior to parts
such as the above.

I think that battery-operated consumer single-chip gizmos were using a
similar (although probably no band-gap) technique back into the early
80's. At least that was the only way I could figure they were
generating a power-on-reset delay of hundreds of ms. Some of these
worked down below 1.2V. I never did figure out what magic they used
internally (maybe related to, or even exactly the same as, Jim's
mention of an internal charge pump?)

Tim.

 

[Rich Grise]

On Tue, 22 Feb 2005 04:10:28 +0000, Paul Rako wrote:

POR circuits are NOT trivial to design. Many people
have crashed and burned using latches, 555 timers and
other schemes. This is why Maxim can get 50 cents for
a reset chip. I have been told by very smart people that
the only valid approach to a POR circuit is a transistor-
level approach. You have to have fully characterized
transistor models if you expect to SPICE it, macromodels
will not do. Be sure to exercise the circuit (reality preferred
to SPICE) for very slow as well as very fast power turn-on and
over a range of temperatures and loads. This is really a
design challenge so don't take it lightly.

What's wrong with a 1 uF cap from the POR pin to ground, with,
say, a 10K pullup?

Thanks,
Rich

 

[Ken Smith]

In article <3h3m11p8e8elj9qficg6souakgqj0nqmui@4ax.com>,
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote:
[...]

A good reset generator will hold reset active for all values of supply
voltage below some threshold all the way down to zero volts,
regardless of dv/dt (except maybe for glitch filtering), and keep
reset active for a certain period (some tens to hundreds of ms) after
the voltage goes above the threshold.

Actually, a good one will hold reset until a number of cycles of the
system clock have gone by. Many parts must be clocked to reset correctly.

--
--
kensmith@rahul.net forging knowledge

 

[Ken Smith]

In article <t9jm11p41336lqrgp8n8g7g5qatrkas8fs@4ax.com>,
Jim Thompson <thegreatone@example.com> wrote:
[...]

I've found a solution I can't divulge at the moment, maybe in two
years, that tracks process corners and times relative to what needs
the reset.

Add a clock monitor input so that you are sure that the system clock is
running before you drop the reset.

I assume you are using a MEMS relay and dashpot so adding a stepper relay
shouldn't be too hard.

--
--
kensmith@rahul.net forging knowledge

 

[Rich Grise]

On Tue, 22 Feb 2005 10:43:35 -0700, Jim Thompson wrote:
....

Digital guys are amusing, aren't they ?

Why, thank you, Jim. That's one of the nicest things I've seen you
write about me (and my kind ;-) ) in quite some time.

Cheers!
Rich

 

[Rich Grise]

On Tue, 22 Feb 2005 11:41:13 -0700, Jim Thompson wrote:

On Tue, 22 Feb 2005 13:27:05 -0500, Keith Williams <krw@att.bizzzz
wrote:

In article <6drm11lo7k4pad5b1rcuooknfh6bqchodh@4ax.com>,
thegreatone@example.com says...
[snip]

My application isn't hot-swap, but it's similar... even has a
charge-pump, which turned out to be helpful in making the POR timing
;-)

Does your charge-pump operate with 1.7V rails? ;-) .25V?

The specification requires 1.65V <= VDD <= 5.5V, over process corners
and -40°C to +105°C

I PASS ;-)

Don't dislocate your shoulder. ;-p

Cheers!
Rich

 

[Ken Smith]

In article <c1vm119m9fhregkak342gsrdupevesdiq6@4ax.com>,
Jim Thompson <thegreatone@example.com> wrote:
[...]

The specification requires 1.65V <= VDD <= 5.5V, over process corners
and -40°C to +105°C

I PASS ;-)

Many FPGA and CPLD circuits do not become sane until the supply voltage
reaches and stays above some voltage. It would be nice if the power on
reset chips also could be used to force the SELF-DESTRUCT signal to ground
and the EXPLODE-IN-FLAMES/ signal near Vcc until after the RESET is over
and then glitch free connect them to the signals from the CPLD.

--
--
kensmith@rahul.net forging knowledge

 

[Keith Williams]

In article <c1vm119m9fhregkak342gsrdupevesdiq6@4ax.com>,
thegreatone@example.com says...

On Tue, 22 Feb 2005 13:27:05 -0500, Keith Williams <krw@att.bizzzz
wrote:

In article <6drm11lo7k4pad5b1rcuooknfh6bqchodh@4ax.com>,
thegreatone@example.com says...
[snip]

My application isn't hot-swap, but it's similar... even has a
charge-pump, which turned out to be helpful in making the POR timing
;-)

Does your charge-pump operate with 1.7V rails? ;-) .25V?

The specification requires 1.65V <= VDD <= 5.5V, over process corners
and -40°C to +105°C

I PASS ;-)

I chose .25V because one POR circuit requirement was for an active low
to be guaranteed above a .25V VCC, until the power supply was within
spec and stable for some period. Forcing a low voltage with a .25V
rail, under worst case conditions, wasn't an easy thing to guarantee.

--
Keith

 

[Keith Williams]

In article <n95n11h8okl22dkpafcfk9bcjp78j169gh@4ax.com>,
thegreatone@example.com says...

On Tue, 22 Feb 2005 15:01:49 -0500, Keith Williams <krw@att.bizzzz
wrote:

In article <c1vm119m9fhregkak342gsrdupevesdiq6@4ax.com>,
thegreatone@example.com says...
On Tue, 22 Feb 2005 13:27:05 -0500, Keith Williams <krw@att.bizzzz
wrote:

In article <6drm11lo7k4pad5b1rcuooknfh6bqchodh@4ax.com>,
thegreatone@example.com says...
[snip]

My application isn't hot-swap, but it's similar... even has a
charge-pump, which turned out to be helpful in making the POR timing
;-)

Does your charge-pump operate with 1.7V rails? ;-) .25V?

The specification requires 1.65V <= VDD <= 5.5V, over process corners
and -40°C to +105°C

I PASS ;-)

I chose .25V because one POR circuit requirement was for an active low
to be guaranteed above a .25V VCC, until the power supply was within
spec and stable for some period. Forcing a low voltage with a .25V
rail, under worst case conditions, wasn't an easy thing to guarantee.

A low VTH N-Channel?

Well, it was 30 years ago, so no low Vt's. It wasn't my circuit, but
IIRC Germanium NPNs were the only solution that worked, barely. (and
what a PITA to get them approved, even then). ;-)

My usual way is to generate a LOW for the region VTH < VDD < BG-Ref*
plus a time-out.

* BG-Ref = bandgap reference

Seems reasonable. I guess with a 0Vt you should be able to get a
decent POR circuit.

In this case I need a POR to last until the charge-pump has reached
final value, WITHOUT loading the charge-pump with any current.

If you think the obvious, you will guess my solution, but I can't
confirm or deny it ;-)

Well, I'm one of those humorous digital guys, so what do I know? ...but
if I had to guess, I'd guess a mirror.

--
Keith

 

[Guy Macon]

(Why did you crosspostthis to sci.electronics.cad? There is a
reason why different newsgroups have different names; it is so
that someone interested in electronics CAD does not have to wade
through off-topic posts about electronics design.)

Allan Herriman wrote:

Rich Grise <richgrise@example.net> wrote:

What's wrong with a 1 uF cap from the POR pin to ground, with,
say, a 10K pullup?

Rich, I am unable to tell whether you were being sarcastic, or whether
you really don't know why an RC circuit is a bad reset generator (in
general).

I believe that you are incorrect. An RC circuit is a bad reset
generator in particular applications, not in general. It depends
on the device. Many devices do just fine with an RC. Others do
well with a resistor/capacitor/diode circuit. A few reset just
fine with no external components. Others really need a dedicated IC.

In general, the reset circuit recommended in the datasheet is a
good reset circuit. There are exceptions, but that's the general
rule.

--
Guy Macon <http://www.guymacon.com/>

 

[Guy Macon]

Ken Smith wrote:

So there's another example of a reset that needed to be held and synced.
The fact that Intel provided the function on an external chip says
something, I'm not sure what, about doing it inside the micro.

It says that at some time in the past it was easier to design a
dedicated chip that behaves correctly at all voltages, and it was
easier to design a microprocessor that expects a reset after the
power supply becomes stable.

 

[Guy Macon]

Rich Grise wrote:

I wondered, "WTF MEMS???" so I looked it up.

Sh*t man f*ck - it ain't that far from reality! Nanomachines! Buckytubes!
The one-atom motor!

Or is that a whole nother level of reality?

I have worked on systems (an I don't mean ICs) that have features that
are less than a hundred atoms across, and seen them into mass production.

 

[Guy Macon]

Jim Thompson wrote:

I had a SMPS on a GenRad portable tester that I bragged couldn't be
killed.

So a smart-aleck came along and did a machine-gun staccato with the
ON/OFF switch, and flame erupted ;-)

So I fixed his ass... I added some circuitry to the ON/OFF switch path
that limited the recycle time to a safe value.

So what happened when he did the same thing with the power cord?

 

[Ken Smith]

In article <MPG.1c8559bc64d2deea98993d@news.individual.net>,
Keith Williams <krw@att.bizzzz> wrote:
[...]

I chose .25V because one POR circuit requirement was for an active low
to be guaranteed above a .25V VCC, until the power supply was within
spec and stable for some period. Forcing a low voltage with a .25V
rail, under worst case conditions, wasn't an easy thing to guarantee.

This sounds like a job for a JFET.

--
--
kensmith@rahul.net forging knowledge