Please help

[raghu]

Hi all,

I have done a project in which FPGA implementation is done.I have used
Xilinx7.1i FPGA tool.
I have written code in Verilog. So,I just wanted to know the type of
questions that can be asked in interviews on FPGA's. Is the knowledge
of VIRTEX II architecture enough? What type of questions could be asked
on the synthesis report? What are the things I should be thorough
enough to answer?
May be this kind of questions should not be posted in this forum. I'm
sorry for that.
But please help me regarding this.

Hoping for the positive response.
Thanks a lot in advance.

Regards,
Raghu

 

[Neo]

Yes, you're right this question is not for this forum however I would
like to point out that fpgas dosent only mean xilinx devices though
they are the leaders. Try understanding the principles on which fpgas
are designed and some of their popular methods of implementing
functions like memories and arithmetic hardware, also things like their
pros and cons vis a vis asics and their power consumtion IO's etc
should be noted.

hope this helps

raghu wrote:

Hi all,

I have done a project in which FPGA implementation is done.I have used
Xilinx7.1i FPGA tool.
I have written code in Verilog. So,I just wanted to know the type of
questions that can be asked in interviews on FPGA's. Is the knowledge
of VIRTEX II architecture enough? What type of questions could be asked
on the synthesis report? What are the things I should be thorough
enough to answer?
May be this kind of questions should not be posted in this forum. I'm
sorry for that.
But please help me regarding this.

Hoping for the positive response.
Thanks a lot in advance.

Regards,
Raghu

 

[unfrostedpoptart]

It depends on what's in the include file. If it's just `defines, it can go anywhere, as long as it's included before the macros are used. If it contains code that must be inside a module (e.g. parameters, functions), then the `include has to be inside the module.

David

ps - next time, please try a more descriptive subject than "please help"

 

[m2star]

On Mar 1, 11:07 pm, unfrostedpoptart <da...@therogoffs.com> wrote:

It depends on what's in the include file.  If it's just `defines, it can go anywhere, as long as it's included before the macros are used.  If it contains code that must be inside a module (e.g. parameters, functions), then the `include has to be inside the module.

 David

ps - next time, please try a more descriptive subject than "please help"

thanks man im gonna apply your tips
and btw thanks again for suggestions............

 

[m2star]

hi all please check

"module mian(a,b,c);
//parameter A_width=4;
//parameter D_width=8;
`include "C:\Documents and Settings\abc\Desktop\prectice\info.h"
input [A_width-1:0]a;
input [D_width-1:0]b;
output [D_width-1:0]c;
assign c[D_width-1:0]=b[D_width-1:0];
endmodule"

and info file is like
info.h
"parameter D_width=8;
parameter A_width=4;"

info file is located at mentioned path but I found this error always
** Error: C:/Documents and Settings/abc/Desktop/prectice/main.v(4):
Cannot open `include file "Cocuments and SettingsMOHSIN
GHAFFARDesktopprecticeinfo.h"
im using modelsim 5.7f SE
please reply sooon.................................