Phase frequency detector

[Jim Thompson]

On 27 May 2004 04:32:52 -0700, Winfield Hill
<Winfield_member@newsguy.com> wrote:

Mike Monett wrote...

[snip]
Only two files showed up at this server - parts 2 and 5. The datasheet
does not seem to be available anywhere on the web, and due to its
historical significance, I wonder if Jim would volunteer to post it on
his site?

You're asking me? Anyway, yes the MC4044 has a great 18-page datasheet,
perhaps Jim will grab it from abse (or I can email it) and serve it up,
properly named so search engines can find it. Meantime, anyone wants a
copy, I'll be happy to send one (1.34MB on disk = 1.9MB attachment?),
just email me here, fixing the address, hill_at_rowland-dot-org

Thanks,
- Win

Win,

I have it here in an old Moto PLL data book, but you've created a
perfectly good PDF, and I'm a long way from filling my space
allocation on the website, so I'll put it up on the S.E.D/Schematics
Page of my website.

Thanks for the memories ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Deepthi]

Hi!
I need help understanding why the deadzone of a conventional phase
frequency detector which consists of 6 two input NAND gates and 3
three input NAND gates is high specially when the reset delay path is
large
Deepthi

 

[Mike]

On 25 May 2004 18:09:06 -0700, Deepthi wrote:

I am trying to analyse the working of a conventional phase frequency
detector(NAND based).I would like to know why the deadzone is high for
it specially when the reset delay is large.Please could anyone help me
out with it atleast an article.

There is no dead zone. I've posted my simulated results on abse - if you
don't get abse, here is the raw data - plot it on a log-log plot. I've
measured real PFDs in the past, and obtained similar results (although I
couldn't get down to 10fs in the lab). These are not exotic circuits, and
contain no cleverness.

Time Charge
Diff. Output
(ps) (fC)
0.01 0.001
0.03 0.003
0.1 0.011
0.3 0.034
1 0.113
3 0.338
10 1.123
30 3.428
100 11.229
300 37.325

-- Mike --

 

[Jim Thompson]

On 27 May 2004 04:32:52 -0700, Winfield Hill
<Winfield_member@newsguy.com> wrote:

[snip]

perhaps Jim will grab it from abse (or I can email it) and serve it up,
properly named so search engines can find it.
[snip]
Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

Done.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Mike Monett]

Jim Thompson wrote:

On 27 May 2004 04:32:52 -0700, Winfield Hill
Winfield_member@newsguy.com> wrote:

[snip]
perhaps Jim will grab it from abse (or I can email it) and serve it up,
properly named so search engines can find it.
[snip]
Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

Done.

...Jim Thompson

Great. Thanks to both of you.

Best Wishes,

Mike Monett

 

[Mike Monett]

Mike wrote:

On 25 May 2004 18:09:06 -0700, Deepthi wrote:

I am trying to analyse the working of a conventional phase
frequency detector(NAND based).I would like to know why the
deadzone is high for it specially when the reset delay is
large.Please could anyone help me out with it atleast an article.

There is no dead zone. I've posted my simulated results on abse -
if you don't get abse, here is the raw data - plot it on a log-log
plot. I've measured real PFDs in the past, and obtained similar
results (although I couldn't get down to 10fs in the lab). These
are not exotic circuits, and contain no cleverness.

Hi Mike,

If your charge pump is fast enough to follow the width of the reset
pulse, then you will have no deadband, as your simulation shows.

However, if the charge pump is slower than the reset pulse to the
latches, you will have deadband. This is described in my PLL Data
Recovery patent 3,810,234 (1974)

"The basic configuration of the phase detector includes two D-type
flip-flops with feedback to restore both to the initial state
after both have been clocked. A delay in the feedback path
establishes the minimum time that either flip-flop is in the
clocked state, thus establishing a minimum time that current
sources are switched on."

"The delay is selected to insure that both current sources are
first turned fully on before they are turned off. This feature is
necessary to eliminate dead-band whereby the phase detector does
not respond properly to small phase errors (or time differences)
between the two input signals to the phase detector."

http://www3.sympatico.ca/add.automation/patents/3810234.htm

Thus, adding delay to the feedback path can solve the deadband
problem. This behavior is also described in the Maxim MAX9382 app
note in the section "Eliminating Dead-Band Behavior"

http://www.maxim-ic.com/appnotes.cfm/appnote_number/1130

However, the added delay reduces the maximum operating frequency of
the pfd, as described in the above Maxim app note.

Another solution is to filter the pfd output pulses so the following
integrator does not have to track fast pulses from the pfd. This
approach is described in Jim's MC4044 data sheet in Figure 22 on
page 6-30:

http://www.analog-innovations.com/SED/MC4044_MC4344.pdf

Here, the filter resistor is split in half and a small cap is added
to ground. The error amplifier no longer has to respond to short
pulses, and it can follow the low frequency variations without the
penalty of deadband.

This solution would be essential when operating at very high clock
frequencies. For example, OnSemi has phase/frequency detectors that
operate beyond 2GHz, such as the 100EP40.

Clearly a charge pump is not feasible at these frequencies. The same
solution is shown in Fig. 11 on page 6 where a small ripple filter
is used to remove the fast switching transients from the pfd. Here
are two url's in case the first one doesn't work:

http://www.onsemi.co.jp/pub/Collateral/AND8040-D.PDF
http://home.zcu.cz/fel/kae/aes2/pll/pdf/AND8040-D.pdf

Another solution that has been proposed is to add an offset to the
phase detector to move the quiescent operating point away from zero.
This can work, but it will increase the reference sideband spurs
present in the vco output. An example is shown in Fig. 3 on page 2
of the National Semiconductor app note AN885:

http://www.national.com/an/AN/AN-885.pdf

There still remains an amazing amount of confusion over the
operation of the classic phase frequency detector. For example, one
poster in this thread claimed the pfd could enter a metastable
condition, which would cause errors in the loop. This is echoed in a
post on the SI-LIST:

http://www.freelists.org/archives/si-list/08-2003/msg00314.html

In actual operation, the classic pfd cannot enter a metastable
state. The latches or d-flops can only turn on when a clock pulse
arrives. They are turned off by the reset pulse, which has a width
of twice the prop delay around the path. This guarantees they will
both be reset properly.

Another possible confusion is shown in the datasheet for the Philips
HCT9046A chip:

http://www.philipslogic.com/products/hc/pdf/74hct9046a.pdf

On page 6, they claim that feeding a capacitor with a current source
eliminates the deadband in the phase detector. They show the
resulting performance in Fig. 11 on page 11.

The truth is the cmos current sources still have a turnon and
turnoff delay. If they are faster than the reset pulse from the pfd,
there will be no deadband. But just because it is a current source
feeding a cap does not guarantee this will be true. The prop delay
of the phase detector has to be taken into account.

So if the ic manufacturers can't get it right, it looks like the
confusion over the deadband problem will continue as a topic in the
newsgroup.

Hope this helps!

Best Wishes,

Mike Monett

 

[Winfield Hill]

Jim Thompson wrote...

Thanks for the memories ;-)

Life is good. Memories are good.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

 

[Mike]

On Thu, 27 May 2004 22:30:49 -0400, Mike Monett wrote:

"The delay is selected to insure that both current sources are
first turned fully on before they are turned off. This feature is
necessary to eliminate dead-band whereby the phase detector does
not respond properly to small phase errors (or time differences)
between the two input signals to the phase detector."

It's not necessary to fully turn on _either_ current source, much less both
of them.

Thus, adding delay to the feedback path can solve the deadband
problem. This behavior is also described in the Maxim MAX9382 app
note in the section "Eliminating Dead-Band Behavior"

http://www.maxim-ic.com/appnotes.cfm/appnote_number/1130

This is classic. The author states, "One of the potential shortcomings of
the charge pump-based loop filter arrangement is the minimum pulse width
that the filter inputs can respond to. A typical phase detector output
condition at lock is a series of very short pulses on the "up" and "down"
outputs. If these pulses are too narrow for the loop filter to "see"
then the result will be a loop dead-band characteristic about zero phase."

First, the author defines a pulse width, that the filter can't see, then
shows what happens when the filter doesn't see it.

Second, we're talking about a PFD dead zone, not a charge pump or filter
dead zone. But forget that: even if we extend the argument to charge pumps
and loop filters, the argument is still garbage.

Third, to reset your flip-flops you have to generate positive outputs from
both flops, which have to propagate through an AND gate back to the reset
input. If the AND gate output is high, both inputs are high, and that means
both inputs to your charge pump are high, and that means the charge pump is
doing something. Unless you try really hard, you _can't_ make a reset pulse
so narrow that your charge pump won't respond.

Fourth, I challenge anyone to design a passive loop filter that can't see
an input.

Another solution is to filter the pfd output pulses so the following
integrator does not have to track fast pulses from the pfd. This
approach is described in Jim's MC4044 data sheet in Figure 22 on
page 6-30:

http://www.analog-innovations.com/SED/MC4044_MC4344.pdf

Here, the filter resistor is split in half and a small cap is added
to ground. The error amplifier no longer has to respond to short
pulses, and it can follow the low frequency variations without the
penalty of deadband.

The small capacitor is generally added to reduce ripple. It is as much an
integrator as the large integrating capacitor - either they can both follow
the PFD output pulses or neither one can.

There _are_ potential issues with the circuit shown, but they have to do
with the op-amp, not the loop filter components.

This solution would be essential when operating at very high clock
frequencies. For example, OnSemi has phase/frequency detectors that
operate beyond 2GHz, such as the 100EP40.

Clearly a charge pump is not feasible at these frequencies. The same
solution is shown in Fig. 11 on page 6 where a small ripple filter
is used to remove the fast switching transients from the pfd. Here
are two url's in case the first one doesn't work:

I fail to see why a charge pump is infeasible when an ECL flip-flop is. The
flip-flop is made from charge pumps; the only difference is that the
flip-flop charge pumps aren't driving a loop filter.

Another solution that has been proposed is to add an offset to the
phase detector to move the quiescent operating point away from zero.
This can work, but it will increase the reference sideband spurs
present in the vco output. An example is shown in Fig. 3 on page 2
of the National Semiconductor app note AN885:

http://www.national.com/an/AN/AN-885.pdf

At -78dBc, the spurs are unlikely to be due to forced offset, and the
National App-Note doesn't mention forced offset. I think their performance
is pretty damn good for a PFD _without_ any forced offset.

In actual operation, the classic pfd cannot enter a metastable
state.

Finally, we agree on something.

The latches or d-flops can only turn on when a clock pulse
arrives. They are turned off by the reset pulse, which has a width
of twice the prop delay around the path. This guarantees they will
both be reset properly.

Actually, it doesn't. Just wait until you've built one that doesn't.

-- Mike --

 

[Bill Sloman]

Mike Monett <no@spam.com> wrote in message news:<40B6A459.143F@spam.com>...

Mike wrote:

On 25 May 2004 18:09:06 -0700, Deepthi wrote:

I am trying to analyse the working of a conventional phase
frequency detector(NAND based).I would like to know why the
deadzone is high for it specially when the reset delay is
large.Please could anyone help me out with it atleast an article.

There is no dead zone. I've posted my simulated results on abse -
if you don't get abse, here is the raw data - plot it on a log-log
plot. I've measured real PFDs in the past, and obtained similar
results (although I couldn't get down to 10fs in the lab). These
are not exotic circuits, and contain no cleverness.

<snip>

Another possible confusion is shown in the datasheet for the Philips
HCT9046A chip:

http://www.philipslogic.com/products/hc/pdf/74hct9046a.pdf

On page 6, they claim that feeding a capacitor with a current source
eliminates the deadband in the phase detector. They show the
resulting performance in Fig. 11 on page 11.

The truth is the cmos current sources still have a turnon and
turnoff delay. If they are faster than the reset pulse from the pfd,
there will be no deadband. But just because it is a current source
feeding a cap does not guarantee this will be true. The prop delay
of the phase detector has to be taken into account.

So if the ic manufacturers can't get it right, it looks like the
confusion over the deadband problem will continue as a topic in the
newsgroup.

You should have read a bit more of the Philips data sheet. Their
trick, as detailed on page 8 of the application note, very
specifically in the note on Fig.8 at the bottom of the page, is that
the postive and negative current sources are overlapped by about
15nsec, and their actual claim is that feeding a capacitor with their
pair of overlapped current sources eliminates the deadband, which does
sound consistent with your story.

Are you really claiming that Philips didn't got it right on the basis
of an over-hasty glance at their data sheet? Or do you have more
persuasive evidence, like some measurements on the 9046 in action?

According to Tom Bruhns, Agilent list the 74HCT9046 as one of their
approved parts, so it seems likely that it does what Philips claim.

-------
Bill Sloman, Nijmegen

 

[Ian Buckner]

"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> wrote in message
news:kqsbb05tm9qbhn2fh46icfom6bp0deig95@4ax.com...

On 27 May 2004 03:14:30 -0700, the renowned Winfield Hill
Winfield_member@newsguy.com> wrote:

snip
Yep, 18 chock-filled pages.

Hmm, what's chock anyway? Hmm, chokkefulle. Hmm. Nuts. Hmmmmm.

1 : a wedge or block for steadying a body (as a cask) and holding it
motionless, for filling in an unwanted space, or for blocking the
movement of a wheel

2 : a heavy metal casting (as on the bow or stern of a ship) with
two
short horn-shaped arms curving inward between which ropes or hawsers
may pass for mooring or towing.



Best regards,
Spehro Pefhany

I believe the origin for "chock-full" is when the "wedge" as in Spef's
definition 1 is used to hold shut, for example, the hatch on a ships
hold. If there are so many nuts in there that the chocks
have to be used to force the hatch cover closed.....

Regards
Ian

 

[Winfield Hill]

Bill Sloman wrote...

Mike Monett wrote ...

Another possible confusion is shown in the datasheet for the Philips
HCT9046A chip:

http://www.philipslogic.com/products/hc/pdf/74hct9046a.pdf

On page 6, they claim that feeding a capacitor with a current source
eliminates the deadband in the phase detector. They show the
resulting performance in Fig. 11 on page 11.

The truth is the cmos current sources still have a turnon and
turnoff delay. If they are faster than the reset pulse from the pfd,
there will be no deadband. But just because it is a current source
feeding a cap does not guarantee this will be true. The prop delay
of the phase detector has to be taken into account.

So if the ic manufacturers can't get it right, it looks like the
confusion over the deadband problem will continue as a topic in the
newsgroup.

You should have read a bit more of the Philips data sheet. Their
trick, as detailed on page 8 of the application note, very
specifically in the note on Fig.8 at the bottom of the page, is that
the postive and negative current sources are overlapped by about
15nsec, and their actual claim is that feeding a capacitor with their
pair of overlapped current sources eliminates the deadband, which does
sound consistent with your story.

Are you really claiming that Philips didn't got it right on the basis
of an over-hasty glance at their data sheet? Or do you have more
persuasive evidence, like some measurements on the 9046 in action?

According to Tom Bruhns, Agilent list the 74HCT9046 as one of their
approved parts, so it seems likely that it does what Philips claim.

Mike, I agree with Bill. After some thought, do you as well?

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)