Parallel in, Parallel out shift register

V

Vivek Menon

Guest
I am trying to synthesize and simulate a parallel shift register that keeps shifting the input data as long as the enable pin is active.

entity shift_out is
Port (
--Inputs
clk : in std_logic;
en : in std_logic;
rst : in std_logic;
in1 : in std_logic_vector(31 downto 0);

-- Outputs
shift_val : out std_logic_vector(31 downto 0)
);
end entity shift_out;

architecture arch of shift_out is

signal shift_t1 : std_logic_vector(31 downto 0) := (others => '0');
....
process (clk, rst, in1, en) is
begin
if rst = '1' then
shift_t1 <= (others=>'0');
shift_val <= (others=>'0');
elsif rising_edge(clk) then
if (en = '1') then
shift_t1 <= shift_t1 ror x"10";
shift_t1 <= in1;
end if ;
end if;
end process;

shift_val <= shift_t1;

end arch;

I am confused with the ror approach, I have tried array slicing and that did not simulate as well.
ANy suggestions??
 
On 8 Jun., 02:00, Vivek Menon <vivek.meno...@gmail.com> wrote:
I am trying to synthesize and simulate a parallel shift register that keeps shifting the input data as long as the enable pin is active.

entity shift_out is
        Port (
        --Inputs
        clk     : in std_logic;
    en      : in std_logic;
    rst     : in std_logic;
        in1     : in  std_logic_vector(31 downto 0);

        -- Outputs
        shift_val : out std_logic_vector(31 downto 0)
     );
end entity shift_out;

architecture arch of shift_out is

signal shift_t1   : std_logic_vector(31 downto 0) := (others => '0');
...
        process (clk, rst, in1, en) is
        begin
                if rst = '1' then
                        shift_t1 <= (others=>'0');
                        shift_val <= (others=>'0');
                elsif rising_edge(clk) then
                        if (en = '1') then
                                shift_t1 <= shift_t1 ror x"10";    
                                shift_t1 <= in1;                      
                        end if ;                        
                end if;
        end process;

        shift_val <= shift_t1;

end arch;

I am confused with the ror approach, I have tried array slicing and that did not simulate as well.
ANy suggestions??
Click to expand...
Hi,
What error messages are you getting from the tools?
Have you checked wether the ror function works for the data type you
are using?

Another way to shift/rotate vectors goes like this:

shift_t1 <= shift_t1(shift_t1'length-2 downto 0) &
shift_t1(shift_t1'length-1); -- simple rotate by one, missing an
input, but you can overwrite the LSB

Have a nice synthesis
Eilert
 
On 8 Jun., 02:00, Vivek Menon <vivek.meno...@gmail.com> wrote:
I am trying to synthesize and simulate a parallel shift register that keeps shifting the input data as long as the enable pin is active.

entity shift_out is
        Port (
        --Inputs
        clk     : in std_logic;
    en      : in std_logic;
    rst     : in std_logic;
        in1     : in  std_logic_vector(31 downto 0);

        -- Outputs
        shift_val : out std_logic_vector(31 downto 0)
     );
end entity shift_out;

architecture arch of shift_out is

signal shift_t1   : std_logic_vector(31 downto 0) := (others => '0');
...
        process (clk, rst, in1, en) is
        begin
                if rst = '1' then
                        shift_t1 <= (others=>'0');
                        shift_val <= (others=>'0');
                elsif rising_edge(clk) then
                        if (en = '1') then
                                shift_t1 <= shift_t1 ror x"10";    
                                shift_t1 <= in1;                      
                        end if ;                        
                end if;
        end process;

        shift_val <= shift_t1;

end arch;

I am confused with the ror approach, I have tried array slicing and that did not simulate as well.
ANy suggestions??
Click to expand...
Hi,
What error messages are you getting from the tools?
Have you checked wether the ror function works for the data type you
are using?

Another way to shift/rotate vectors goes like this:

shift_t1 <= shift_t1(shift_t1'length-2 downto 0) &
shift_t1(shift_t1'length-1); -- simple rotate by one, missing an
input, but you can overwrite the LSB

Also there's some big flaw in your approach.
You have no signal to distinguish between load and shift operation.
Enable is working for both actions and so you are only always loading
when enable is active and do not see any effect of the ror function.

Do something like this:
Define a port
load : in std_logic;
and in your enable branch:

if load = '1' then
shift_t1 <= in1;
else -- rotate
shift_t1 <= shift_t1(shift_t1'length-2 downto 0) &
shift_t1(shift_t1'length-1);
end if;

Have a nice synthesis
Eilert
 
Take shift_val out of the clocked process. It should not be assigned
in both the process and the concurrent assignment statement.

Also, remove everything but clk and rst from the process sensitivity
list.

Andy
 
Vivek Menon wrote:

I am trying to synthesize and simulate a parallel shift register that
keeps shifting the input data as long as the enable pin is active.

entity shift_out is
Port (
--Inputs
clk : in std_logic;
en : in std_logic;
rst : in std_logic;
in1 : in std_logic_vector(31 downto 0);

-- Outputs
shift_val : out std_logic_vector(31 downto 0)
);
end entity shift_out;

architecture arch of shift_out is

signal shift_t1 : std_logic_vector(31 downto 0) := (others => '0');
...
process (clk, rst, in1, en) is
begin
if rst = '1' then
shift_t1 <= (others=>'0');
shift_val <= (others=>'0');
elsif rising_edge(clk) then
if (en = '1') then
shift_t1 <= shift_t1 ror x"10";
shift_t1 <= in1;
end if ;
end if;
end process;

shift_val <= shift_t1;

end arch;

I am confused with the ror approach,
Click to expand...
Me too. What ror operator? What packages are you using? The only ror
operator that I know of is from ieee.numeric_std:

------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987
-- compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)

------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987
-- compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)


I have tried array slicing and that did not simulate as well.
ANy suggestions??
Click to expand...
Posting error messages would be nice. Or observed/expected behaviour.

I also suspect a missing else:

if (en = '1') then
shift_t1 <= shift_t1 ror x"10";
else --< !!
shift_t1 <= in1;
end if;

And for the shift operation I would suggest something like:

shift_t1 <= shift_t1(shift_t1'low) &
shift_t1(shift_t1'high downto shift_t1'low+1);

Which is the same as

shift_t1 <= shift_t1(0) & shift_t1(31 downto 1);

without the hard coded numbers.

For the rest: remove 'in1' and 'en' from the sensitivity list. They are not
needed.

Oh, and resetting shift_val is not needed: it is not a flip-flop, shift_t1
is. And why using shift_t1 at all? Why not just shift_val? There is no need
for the extra signal.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
On Jun 7, 8:00 pm, Vivek Menon <vivek.meno...@gmail.com> wrote:
I am trying to synthesize and simulate a parallel shift register that keeps shifting the input data as long as the enable pin is active.
Click to expand...
Have you simulated your design and does it work as intended? If not,
then get that working before synthesizing. If so, then I'm surprised
because...

<snip>
if (en = '1') then
  shift_t1 <= shift_t1 ror x"10";
    shift_t1 <= in1;
Click to expand...
The second assignment to shift_t1 will override the first assignment.
The net of all this is that the assignment with the 'ror' won't do
anything.

I am confused with the ror approach, I have tried array slicing and that did not simulate as well.
Click to expand...
Until you get the simulation working properly, it will likely not make
much sense for you to try to synthesize. You have a basic issue with
your design in that you don't have a method for loading and for
shifting the data. Typically one would have a 'load' and a 'shift'
input but it might be that you intend to load any time you're not
shifting in which case you should have written

if (en = '1') then
shift_t1 <= shift_t1 ror x"10";
else -- KJ added
shift_t1 <= in1;
....

ANy suggestions??
Click to expand...
Also, the 'ror' function is defined for unsigned types, not
std_logic_vector.
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED;

I would suggest changing the data type of shift_t1
shift_t1 : unsigned(31 downto 0);

Then convert to/from std_logic_vectors on the various assignments.

Also see Andy's suggestions. To have the compiler catch the first
error that Andy pointed out, consider using std_ulogic rather than
std_logic.

Kevin Jennings
 
Thanks for the tips, I was trying to synthesize a shift register using array slicing. Since that was not working, I tried all the remaining options, ror, sra, srl, etc.

Here's how I did it finally:

architecture arch of shift_out is

-- Signals
signal shift_t1 : std_logic_vector(1727 downto 0) := (others => '0');

begin

process (clk, rst) is
begin
if rst = '1' then
shift_t1 <= (others=>'0');
elsif rising_edge(clk) then
if (load = '1') then
shift_t1 <= in1;
elsif (shift_en ='1') then
shift_t1 <= shift_t1(15 downto 0) & shift_t1(1727 downto 16);
end if ;
end if;
end process;

shift_val <= shift_t1(15 downto 0);

end architecture arch;
 
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