Overflow on INTEGER value.

[Andy]

I only use slv for top-level (device) ports, and that's only so that the gate level and RTL ports are the same. All other entities and ports use unsigned anywhere an slv would have been called for. An unsigned can do everything an SLV can do, and more!

I use a lot of integers too. I like that x + 1 > x is always true, or it is an assertion failure (when x = integer'high). Note that the above is true even if x = x'subtype'high, assuming x'subtype'high < integer'high.

Andy

 

[rickman]

On 10/11/2012 8:19 AM, Luis Cupido wrote:

Where do you find these conversion functions to_unsigned and
to_stdlogicvector? I don't think they are part of numeric_std. Maybe you
have too many libraries loaded and aren't keeping them all straight?

Rick

I just have:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

the to_unsigned() yes is part of numeric_std,
the to_stdlogicvector() I saw on the web but after
your post I was looking inside the libs that came with Quartus and
You're right that one is not there.

on the numeric_std that came with quartusII it is now very clear that
to_signed() and to_unsigned() functions are for converting integers
only. period !

Yes, because t0_unsigned is not needed to convert slv. They are
"closely related" types and so the "cast" works to convert them. I
sometimes forget my VHDL terminology but the concept is right.

The origin of all confusion was found here on the web
lines 626 and following where all those stuff for std_logic_vectors also
exists.
Apparently existed in 1994 and were taken out in 1995... :-(

http://www.ece.msstate.edu/~reese/EE8993/ieee_standards/numeric_std.vhd

sometimes the web is a bad place to look for info :-(

Oh, yes, an old document can be misleading. I always have to search my
hard drive to find my copies of numeric_std which is in the synthesis
vendor's directories. That is the one that matters when you are working
with their tools and you don't even need to be online.

Glad you got to the bottom of all this. I think you wrapped your head
around it faster than I did.

There is another case where an expression is of indeterminate type. I
can't say this is a valid case, but supposed + is defined for both
unsigned result and a signed result for the operands you are using.
Then the type of the result has to be specified. I believe this is done
with signed' in front of the expression (in parentheses of course).
Maybe someone has a real example?

So there are three ways you indicate type of expressions, this is one
(not sure what it is called), then there is the conversion of closely
related types (free compared to a conversion function) and finally there
are conversion functions like to_integer() which require a function to
be written. I think that covers the field.

Rick

 

[rickman]

On 10/11/2012 7:05 PM, Andy wrote:

Rick,

type_name'(expression) is called a qualified expression. It explicitly tells the compiler that the expression IS of type type_name. This is used, as in your example, when the result of a function/operation is ambiguous. These are often confusing, since such an ambigous expression will work if assigned directly to an object or associated with a port (which always has a defined type). Ambiguous expressions often involve literal expressions like (7 downto 0 => '0'), in contexts where there are multiple available types that fit the literal expression. No type conversion is involved in a qualified expression.

type_name(expression) is a built-in type conversion function that automatically exists between closely related types (aggregates whose elements are of the same base type). This is as close to a "cast" as vhdl gets.

conversion_function_name(expression) is an explicit type conversion function that has to be written and compiled, and can convert between any two types.

Hope this helps,

Andy

That's great Andy. Thanks.

Rick

 

[Andy]

Rick,

type_name'(expression) is called a qualified expression. It explicitly tells the compiler that the expression IS of type type_name. This is used, as in your example, when the result of a function/operation is ambiguous. These are often confusing, since such an ambigous expression will work if assigned directly to an object or associated with a port (which always has a defined type). Ambiguous expressions often involve literal expressions like (7 downto 0 => '0'), in contexts where there are multiple available types that fit the literal expression. No type conversion is involved in a qualified expression.

type_name(expression) is a built-in type conversion function that automatically exists between closely related types (aggregates whose elements are of the same base type). This is as close to a "cast" as vhdl gets.

conversion_function_name(expression) is an explicit type conversion function that has to be written and compiled, and can convert between any two types.

Hope this helps,

Andy

 

[Luis Cupido]

.....
Hope this helps,

Andy

That's great Andy. Thanks.

Rick

Great help folks. Thanks.
I saw here a quantum leap on my knowledge.
I believe I can easily start using numeric_std
without much issues. (I already started).

Many thanks.

Luis C.

p.s. Yes I've seen also the qualified expression thing
but only now become clear what it does. tks.

 

[Alan Fitch]

On 12/10/12 02:53, Luis Cupido wrote:

.....
Hope this helps,

Andy

That's great Andy. Thanks.

Rick

Great help folks. Thanks.
I saw here a quantum leap on my knowledge.
I believe I can easily start using numeric_std
without much issues. (I already started).

Many thanks.

Luis C.

p.s. Yes I've seen also the qualified expression thing
but only now become clear what it does. tks.

I'm going to indulge in a bit of advertising and point you to

http://www.doulos.com/knowhow/vhdl_designers_guide/numeric_std/ and the
handy chart of conversions on that page.

regards
Alan


--
Alan Fitch