others and unconstrained array

M

MariuszK

Guest
Hello,

I have following error in line "out1 <= (others=>'0');"
BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
array aggregate.

If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
everything work. How can I change below code to have universal
unconstrained buffer with reset?

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BuffG is
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE : in STD_LOGIC;
in1 : in STD_LOGIC_Vector;
out1: out STD_LOGIC_Vector
);
end BuffG;

architecture BuffG of BuffG is
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
out1 <= (others=>'0');
elsif CE = '1' then
out1 <= in1;
end if;
end if;
end process;
end BuffG;
 
"MariuszK" <mariusz.kwiczala@gmail.com> wrote in message
news:58dc006e-749f-46ef-b310-b18217530d4d@h5g2000yqh.googlegroups.com...
Hello,

I have following error in line "out1 <= (others=>'0');"
BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
array aggregate.

If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
everything work. How can I change below code to have universal
unconstrained buffer with reset?
Click to expand...
One way would be by adding a function, either in the architecture or the
process, see below.

architecture BuffG of BuffG is
begin
process(CLK)
function Zeroit(V: std_logic_vector) return std_logic_vector is
variable RetVal: std_logic_vector(V'range) := (others => '0');
begin
return(RetVal);
end function Zeroit;
begin
if rising_edge(CLK) then
if RST = '1' then
out1 <= (others=>'0');
elsif CE = '1' then
out1 <= in1;
end if;
end if;
end process;
end BuffG;

KJ
 
"MariuszK" <mariusz.kwiczala@gmail.com> wrote in message
news:58dc006e-749f-46ef-b310-b18217530d4d@h5g2000yqh.googlegroups.com...
Hello,

I have following error in line "out1 <= (others=>'0');"
BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
array aggregate.

If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
everything work. How can I change below code to have universal
unconstrained buffer with reset?
Click to expand...
Another method is to define a constant inside the process or architecture
that is of the same size, see below.

architecture BuffG of BuffG is
begin
process(CLK)
constant Zeros: std_logic_vector(out1'range) := (others => '0');
begin
if rising_edge(CLK) then
if RST = '1' then
out1 <= Zeros;
elsif CE = '1' then
out1 <= in1;
end if;
end if;
end process;
end BuffG;

KJ
 
"MariuszK" <mariusz.kwiczala@gmail.com> wrote in message
news:58dc006e-749f-46ef-b310-b18217530d4d@h5g2000yqh.googlegroups.com...
Hello,

I have following error in line "out1 <= (others=>'0');"
BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
array aggregate.

If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
everything work. How can I change below code to have universal
unconstrained buffer with reset?
Click to expand...
One way would be by adding a function, either in the architecture or the
process, see below.

architecture BuffG of BuffG is
begin
process(CLK)
function Zeroit(V: std_logic_vector) return std_logic_vector is
variable RetVal: std_logic_vector(V'range) := (others => '0');
begin
return(RetVal);
end function Zeroit;
begin
if rising_edge(CLK) then
if RST = '1' then
out1 <= Zeroit(out1);
elsif CE = '1' then
out1 <= in1;
end if;
end if;
end process;
end BuffG;

KJ
 
MariuszK <mariusz.kwiczala@gmail.com> wrote in news:58dc006e-749f-46ef-
b310-b18217530d4d@h5g2000yqh.googlegroups.com:

Hello,

I have following error in line "out1 <= (others=>'0');"
BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
array aggregate.

If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
everything work. How can I change below code to have universal
unconstrained buffer with reset?

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BuffG is
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
CE : in STD_LOGIC;
in1 : in STD_LOGIC_Vector;
out1: out STD_LOGIC_Vector
);
end BuffG;

architecture BuffG of BuffG is
begin
process(CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
out1 <= (others=>'0');
elsif CE = '1' then
out1 <= in1;
end if;
end if;
end process;
end BuffG;
Click to expand...

Change the line:
out1 <= (others=>'0');

to:
out1 <= (out1'range =>'0');

Regards,
Allan
 
On 23 Lis, 03:42, Allan Herriman <allanherri...@hotmail.com> wrote:
MariuszK <mariusz.kwicz...@gmail.com> wrote in news:58dc006e-749f-46ef-
b310-b18217530...@h5g2000yqh.googlegroups.com:





Hello,

I have following error in line "out1 <= (others=>'0');"
BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
array aggregate.

If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
everything work. How can I change below code to have universal
unconstrained buffer with reset?

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity BuffG is
   port(
      CLK : in  STD_LOGIC;
      RST : in  STD_LOGIC;
      CE  : in  STD_LOGIC;
      in1 : in  STD_LOGIC_Vector;
      out1: out STD_LOGIC_Vector
      );
end BuffG;

architecture BuffG of BuffG is
begin
   process(CLK)
   begin
      if rising_edge(CLK) then
         if RST = '1' then
            out1 <= (others=>'0');
         elsif CE = '1' then
            out1 <= in1;
         end if;
      end if;
   end process;
end BuffG;

Change the line:
            out1 <= (others=>'0');

to:
            out1 <= (out1'range =>'0');

Regards,
Allan- Ukryj cytowany tekst -

- Pokaż cytowany tekst -
Click to expand...
Thank you All!
Attribute "'range" that's it what I need.

Best Regards,
Mariusz
 
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