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1 Lucky Texan
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On Jul 14, 6:19 pm, Roberto Waltman <use...@rwaltman.com> wrote:
syncing a scope with a 'control' signal could've been just as useful
(in examining the width of a port or buffer anyway). Anyway, we used
it as a poorman's logic analyzer, in the distant past. lol! I CAN see
how a slow clock could be useful too. Especially with limited test
equipment.
It seems to me, some looping test programs coupled with externallyMichael S wrote:
glen herrmannsfeldt wrote:
How about 1uHz? (or 1nHz or 1pHz?)
...
For 1uHz, R=1Mohm, C=1F. That isn't easy, even with an external
capacitor!
...
I can imagine the utility of 1mHz, may be, even 0.1 mHz in some
extreme cases where you want to take a deep thought between the
clocks. But 1uHz? Can't see how it helps debugging.
Reading 1uHZ as "full stop",...
A few geological ages ago, I was debugging a quite complex system
based on a Z80 CPU (Fully static design)
Things like an ICE or logic analyzer were luxuries not available to
me, so I had to improvise.
One of the things I did was to hook up a couple of logical gates and a
flip-flop between the RD & WR lines and the WAIT lines, forcing the
CPU into wait state each time it tried to access the bus.
The address and data lines were connected to 3 x 8-bit buffers,
multiplexing the 24 bits into a single 8-bit lane.
That lane plus a few control lines went to a CP/M computer printer
port, where an interpreted BASIC program read the data and then
toggled the flip-flop allowing the Z80 to do one more memory cycle.
The basic program would disassemble the current operation and, if it
involved an external memory transfer show exactly what was being
read/written and where
Voila! With an investment of a few hours of work I had a system that
allowed me to fully trace the program flow and memory access.
Could have any number of breakpoints (just keep toggling the flip-flop
until reaching a given address, then stop for manual control), count
the number of times a branch was taken, etc.
Everything in slow motion, of course, but the information I gathered
was not available otherwise.
I was forcing wait states, but could have accomplished the same thing
gating the CPU clock.
Either technique would have been impossible with chips like the
6800/6502 that would loose state if the clock was below a certain
minimum frequency, and that could not be kept in wait state for more
than a few microseconds.
You can not do the same with a modern controller with on-chip memory,
etc. but still, slowing down the processor so that you can, for
example, check the state of 10 GPIO pins with your 2-channel scope, is
a very valuable feature.
syncing a scope with a 'control' signal could've been just as useful
(in examining the width of a port or buffer anyway). Anyway, we used
it as a poorman's logic analyzer, in the distant past. lol! I CAN see
how a slow clock could be useful too. Especially with limited test
equipment.