NFA FSM

Hi Guys!
I am trying to code the following sequential re-coder/scrambler FSM in VHDL.

000 -> 110
001 -> 101
010 -> 111
011 -> 110
100 -> 010
101 -> 011
110 -> 010
111 -> 000

I understand this is an NFA and must be converted to DFA before implementing.

I was able to convert into a DFA, but I am not sure how to assign the output for the merged states. Help on this would be appreciated.

 

[Thomas Stanka]

Am Sonntag, 19. Oktober 2014 21:33:58 UTC+2 schrieb mohitk...@gmail.com:

I am trying to code the following sequential re-coder/scrambler FSM in VHDL.
[..]
I understand this is an NFA and must be converted to DFA before implementing.

Why? Please explain on which details of the function you see the nondeterminstic behavior.

In fact you have several possibilities, but I would use for the simple function above a lookup table. If you consider the input as unsigned you could just say that 0 => 110, 1 => 101 and so on, the conversion is than just a lookup. Ofc you could also try to use karnaugh map to reduce the lookup youself, but I'm sure for 3 bit input your sythesis tool will find best solution.

regards Thomas

 

[Tobias Baumann]

I also would implement it as a LUT. But input 100 and 110 has the same
output. I think one of both should be 001 on output. Then it seems a bit
like Gray Counter, going backward.

Best regards,
Tobias