New to FPGA, seeking advice

[Ray Andraka]

SRL16's are fine for muxes that are relatively static. I wouldn't use them in
a barrel shift used for floating point normalize or denormalize though, as it
takes 16 clocks to change it. If you have that much time between samples and
are that concerned about area, you should be doing bit or digit serial logic.

As long as you are keeping the floating point reasonable, the barrel shifts are
not too bad. Reasonable means maybe 12-16 bits mantissa and a few bits of
exponent. In most cases, you don't need full IEEE floating point. Another
trick I use frequently is to do a series of operations treating the mantissa a
fixed point and renormalizing after the series instead of after each
operation. This saves quite a bit of area and latency that would otherwise be
needed for de/re-normalizing. Block floating point works well in situations
where the dynamic range within a block of data is small but you don't know
apriori what the scaling will be. This is often used in FFTs.

Glen Herrmannsfeldt wrote:

"Ray Andraka" <ray@andraka.com> wrote in message
news:3F579ECC.D5C92BF@andraka.com...
Actually, the xilinx structure can make a very efficient cross bar. One
way is
to do a partial reconfiguration to switch the crossbar connections, in
which
case it uses mostly just the routing resources, not CLBs. If partial
reconfiguration is not your cup of tea, you can make efficient 4:1 muxes
using
SRL16's. These take 16 clocks to reroute, and require a simple loader
which can
be shared among many bits, but they are compact and fast.

A subject that comes up reasonably often is doing floating point arithmetic
in FPGA's. For example, as a systolic array. The
prenormalization/postnormalization for floating point add/subtract, using
barrel shifters in CLB's are so big that it is just about impractical. I
was considering the crossbar switch as an array of muxes, which would also
be huge.

I do believe that reconfiguration is too slow for floating point
normalization, but maybe the SRL16's.

There is something called block floating point (I have never used it) where
you have a whole array that has one characteristic but different mantissa
for each element. (Apparently very useful for some algorithms.) In that
case, the 16 clocks to load the SRL16's might be fast enough for a whole
array of numbers. Post normalization could still be a problem, though.

-- glen

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Anil Khanna]

Hi Brian,

Taking a step back from FPGAs, I would investigate specific programmable
cross-point switches that Lattice offers for this kind of funtionality.
Check out the ispGDX family from Lattice - you might be surprised!

http://www.latticesemi.com/products/digin/ispGDX/index.cfm

Anil


"Brian Fairchild" <spam.spam@spam.com> wrote in message
news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com...

Hi

I'm an embedded systems designer who feels that it's about time he
started to learn about using FPGAs. I'm happy using PLDs, designed in
something like CUPL but don't know where to start on bigger devices.

I only have a small budget for development tools and I'm in the UK.

From what I can see my best choice of manufacturer is probably down to
Xilinx or Altera.

Can anyone suggest an evaluation board that would get me started?

I see that devices are sold in terms of their gate count. How
efficient is a typical design? For instance, if I want to make a 16 by
16 CPU controlled crosspoint how many FPGA gates will I need? I can
see that I need 16 OR gates each with 16 AND array inputs for the
output terms, 64 latches to store the selection and some more gates to
do the latch address decoding. Is there any easy way to choose the
right part?

Thanks

Brian
--
Brian Fairchild
B dot Fairchild at Dial dot Pipex dot Com

"But apart from that Mrs Lincoln, how did you enjoy the play?"

 

[Austin Lesea]

Allan,

Correct!

It was in New York before 1900 that the first buried lines were used, and if the battery was negative ground, the copper migrated away from the
wires into the ground if there was leakage (which there always was with handwrapped cotton insulated wire cables...).

When they flipped the ground to positive, the wires got fatter (with metal salts from the ground) and leakier, but they lasted longer.

Austin

Allan Herriman wrote:

On Thu, 04 Sep 2003 14:32:15 -0700, Austin Lesea
Austin.Lesea@xilinx.com> wrote:

Tom,

Although the x-bar relays were bi-directional, they were only used in a uni-directional fashion for toll switching (full duplex four wire).
The only bidirectional metallic stage was the first level concentrator for the phone lines to the subscribers with the x-bar 5 WeCo Class 5
office. After that, the circuits were separated into transmit and receive.

The older Strowger step by step relays were bidirectional switching from subsrciber to subscriber, and four wire for toll circuits.

Telco lore bonus question: why is positive ground battery used in telecom?

The voltage is negative with respect to ground to help reduce
corrosion problems.

-48V is the standard voltage used in phone exchanges. (Actually
it's more like -52V when float charging, but you get the idea.)
(ETSI standard ETS 300 132-2 says -40,5 to -57,0 Vdc at the equipment
input. A "slight degradation in performance" may exist for voltages
in the range -40,5 to -44,0 Vdc. Telcordia will have similar specs.)

The magnitude of the voltage is 48V because that voltage is a good
compromise between a number of factors, one major one being the
ability to drive enough power down a long (high resistance) line to
the phone. Really old phone exchanges needed a certain loop current
to activate the hook relay.

ISDN lines are usually biased at a higher voltage which can be up to
120V (max allowable for TNV), as the ISDN equipment needs more power.

Note that some areas use -60V (= 5 x 12V) for POTS.

Regards,
Allan.

Inter-office tie trunk tivia: a revertive dial trunk line would dial the foreign office by initiating the call, and telling the foreign
office to start dialing. When the foreign office had dialed the right number of digits, the local office would signal it to stop, and go on
to the next digit.

Extra point question: which class 5 local electronic office switch was demanded by a PUC/PSC to be removed from service due to incredibly
poor performance? What state's PUC/PSC?

Austin

Tom Seim wrote:

"Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:<5TL5b.137460$JA5.3292926@news.xtra.co.nz>...
"Brian Fairchild" <spam.spam@spam.com> wrote in message
news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com...

efficient is a typical design? For instance, if I want to make a 16 by
16 CPU controlled crosspoint how many FPGA gates will I need? I can
see that I need 16 OR gates each with 16 AND array inputs for the
output terms, 64 latches to store the selection and some more gates to
do the latch address decoding. Is there any easy way to choose the

Just as an academic thing for myself.

Is a bi-directional crosspoint switch able to be produced with a FPGA? My
understanding is they are a matrix of fets each one having a memory cell to
store it's setting.

So I would say that it was impossible. Even a fully digital one would still
require that an an I/O pin can be used for input and output at the same
time.

Can anyone confirm or deny?

Deny.

Crossbars are uni-directional. Now, the REAL relay crossbars used by
the telcos upto the 1970s ARE bi-directional.