negative slack

[sagar g]

hello everyone
When I synthesize my code using synplify I got a slack of -40.508 on a instance of type DFN, pin Q and its arrival time is 1.395.
how can i reduce that slack please help.
where should I modify my code
why is this slack introduced in my code I'm a newbie to vhdl please help
I'm written code for SDI-12 protocol, it shows correct simulation results in pre synthesis simulation & 'X' through out the simulation in post synthesis simulation on output signals. are the negative slacks on many instances is the reason for that 'X' please help

thanks in advance

 

[rickman]

On 9/12/2012 1:34 AM, sagar g wrote:

hello everyone
When I synthesize my code using synplify I got a slack of -40.508 on a instance of type DFN, pin Q and its arrival time is 1.395.
how can i reduce that slack please help.
where should I modify my code
why is this slack introduced in my code I'm a newbie to vhdl please help
I'm written code for SDI-12 protocol, it shows correct simulation results in pre synthesis simulation& 'X' through out the simulation in post synthesis simulation on output signals. are the negative slacks on many instances is the reason for that 'X' please help

thanks in advance

The timing analysis is done on the design files that describe how your
design will be implemented in the FPGA. Once those decisions have been
made the timing of the signal paths can be measured which is what static
timing analysis is about. They calculate the timing between every two
endpoints in your design and show you the ones that don't meet the
requirements.

The negative slack means the signal path is taking too long and is not
as fast as your clock. You can slow down the clock, likely not an
option in your case, or you need to figure out what the delay path is so
slow. There are tools for looking at what has been synthesized, none of
them fun to use in my opinion, and you need to figure out if the
synthesized logic was inefficient or if you are doing a bad job of coding.

How much code are you dealing with? Could you post it here?

Rick

 

[Andy]

Slack is a method of accounting for whether or not the actual propagation delay between registers (clk2out, routing, LUT delays, setup, etc.) is less than the clock period. Negative slack indicates the delay is too long (or clock period too short). Positive slack indicates the delay is fast enough (or the clock period is long enough) to allow the data to propagate between registers correctly.

For a given logic path between registers, the total slack for the whole path is usually annotated on each element, even though it is only partially due to any one element.

Usually, negative slack annotated on a Q pin of a FF indicates the path FROM that FF TO another (or same) FF input is too slow.

A couple of things to consider: This is a synthesis warning, so it includes a pre-place&route estimate of the routing delay(s) between logic elements. This estimate may be slower or faster than the real, post-P&R routing delay.

Second, make sure you have specified for the synthesis tool what your clock period actually will be for this clock.

Otherwise, negative slack is usually corrected by reducing the logic that has to be performed between the two registers.

If your synthesis tool supports it, you may also try enabling the "retiming" optimization option. This optimization shifts logic from paths that have negative slack to adjacent paths (before/after the source/destination FF) that have positive slack. It will affect the behavior of registers in your design, but inputs and outputs would not be affected. Read up on how to specify this option, and how to constrain it so it does not affect critical registers (like synchronizers, etc.)

Hope this helps,

Andy