need small PAL with SR latch

[colin]

"keith" <krw@att.bizzzz> wrote in message
newsan.2005.06.26.16.07.02.195114@att.bizzzz...

On Sat, 25 Jun 2005 18:16:56 +0000, colin wrote:

Perhaps something like...
(r,s, and q are standard_logic or standard_ulogic)

SRLatch: Process (S,R) -- Set dominant SR latch
BEGIN
IF s = '1' -- Set is dominant
THEN q <= '1';
ELSE IF r = '1'
THEN q <= '0';
END IF;
END PROCESS;

I tried this, it cleverly sees theres a SR latch here and goes ahead and
uses one but then gives an error :-
'xxx devices do not have latch with both async set and reset. Fitter may
fail' (wich it does)

Il gues il stick to schematic entry as this seems to work although I still
havnt figured out how to stop it using negative logic on the outputs with
some devices.

Colin =^.^=

 

[keith]

On Sun, 26 Jun 2005 20:06:16 +0000, colin wrote:

"keith" <krw@att.bizzzz> wrote in message
newsan.2005.06.26.18.14.06.823026@att.bizzzz...

big snip

Oh, *now* the light goes on. I thought your design came out with 100
pins. Yes, FPGAs are going to have a lot of pins. ;-)



Its amasing just how many pins some of theses devices have, and with oudles
of gates too and 400mhz clock speed etc, and yet they stil dont consume that
much more power than some of the small ones.

Im realy tempted to try and do something neat to do with all those pins but
cant think of anything right now.

Crap. I've never had enough pins. Even an FG680 ran out of pins (five
years ago).

Not necessarily more idiot-proof, but clocked logic can be simulated
and timed. Asynchronous logic and loops in logic are nightmares.

Yes its easy to verify setup times are met with clocked logic as everything
just adds up between the edges.

It's not just "easy" it's "possible".

Metastable states in asynch loops can cuase nightmares but they still have
defineable boundries, the latches in the macro cells have internal async
loops hence the setup and min clock width timings inorder to avoid
metastable states but it is much more controled as they will only have 2
adjacent virtualy unloaded gates in the loop.

Actually, no they don't. You have no idea whether your routing this time
is the same as last. Metastapility is a horrid thing when you have no clue
what your feedback time is. That's just one of the heads of the FPGA
hydra.

In logic wich has numerous feedback loops all the possible circular
paths can be very complex and hard to ensure metastable (or race
conditon) states are avoided, but as the theory is reasonably simple a
computer should be able to handle the complexity, but it seems the tools
are made to do it the easy way.

Not so, grasshopper. It's not even possible to know. All you're doing is
opening the window of death. ...and not knowing how wide!

However it seems high speed clocks accross large chips are cuasing
problems and theres interest in using more asycnhrounous techniques such
as mixed non synchronised clock systems however these seem to cuase as
much problems, if you could make a microprocessor internaly completly
asynchronous (with of course suitablly generated handshaking for every
movement of data) it would avoid clock issues altogether.

Naw. We haven't gotten there yet. Clocks are still distributed in a sane
manner and even taken care of in the timing analysis. ...you add your
loops, and all bets are off!

You need to know what is in the library though. I try not to do this
because it messes up the VHDL and makes it less portable. When I find
it necessary, I keep all such instantiations in seperate files and mark
them as being technology dependent.

ah yes of course, il have a look to see if there are any asycnhrounous
sr latches already there

The may be, but I doubt it. As Iv'e said, these are an anethma to logic
design. ...not to mention test.

I found VHDL, at least the synthesizable subset, to be very easy to
learn. Much of the difficulty is in knowing what synghesis is going to
do with your source code. Synthesis matches templates, so your job,
should you choose to accept, ;-) is to learn what templates turn out
what logic.

That reminds me of trying to use high level languages in multi tasking
embeded systems.

VHDL *is* essentially a multi-threadded language. The point of the
PROCESS statement is to serialise execution. The last to set a
signal/variable in a process rules though (bottom to top, as it were).

--
Keith

 

[keith]

On Sun, 26 Jun 2005 21:49:50 +0000, colin wrote:

"keith" <krw@att.bizzzz> wrote in message
newsan.2005.06.26.16.07.02.195114@att.bizzzz...
On Sat, 25 Jun 2005 18:16:56 +0000, colin wrote:

Perhaps something like...
(r,s, and q are standard_logic or standard_ulogic)

SRLatch: Process (S,R) -- Set dominant SR latch
BEGIN
IF s = '1' -- Set is dominant
THEN q <= '1';
ELSE IF r = '1'
THEN q <= '0';
END IF;
END PROCESS;

I tried this, it cleverly sees theres a SR latch here and goes ahead and
uses one but then gives an error :-
'xxx devices do not have latch with both async set and reset. Fitter may
fail' (wich it does)

You don' thave the latch in the library (which I suspected). It appears
that it's not smart enough to make one out of gates. Synplify would, but
bitch like hell doing it. There is a difference in tools.

Il gues il stick to schematic entry as this seems to work although I
still havnt figured out how to stop it using negative logic on the
outputs with some devices.

Look at you IOBs. You may have an IOB that has an implied inversion. The
Xilinx IOBs were a littttle crazy with OE's, it wouldn't surprise me that
Altera had similar nonsense.

--
Keith

 

[colin]

"keith" <krw@att.bizzzz> wrote in message
newsan.2005.06.26.23.39.29.932032@att.bizzzz...

On Sun, 26 Jun 2005 21:49:50 +0000, colin wrote:

"keith" <krw@att.bizzzz> wrote in message
newsan.2005.06.26.16.07.02.195114@att.bizzzz...
On Sat, 25 Jun 2005 18:16:56 +0000, colin wrote:

Perhaps something like...
(r,s, and q are standard_logic or standard_ulogic)

SRLatch: Process (S,R) -- Set dominant SR latch
BEGIN
IF s = '1' -- Set is dominant
THEN q <= '1';
ELSE IF r = '1'
THEN q <= '0';
END IF;
END PROCESS;

I tried this, it cleverly sees theres a SR latch here and goes ahead and
uses one but then gives an error :-
'xxx devices do not have latch with both async set and reset. Fitter may
fail' (wich it does)

You don' thave the latch in the library (which I suspected). It appears
that it's not smart enough to make one out of gates. Synplify would, but
bitch like hell doing it. There is a difference in tools.

Il gues il stick to schematic entry as this seems to work although I
still havnt figured out how to stop it using negative logic on the
outputs with some devices.

Look at you IOBs. You may have an IOB that has an implied inversion. The
Xilinx IOBs were a littttle crazy with OE's, it wouldn't surprise me that
Altera had similar nonsense.

Thanks, I'm using Lattice as Altera doesnt seem to do the small parts,
it seems to use the synplify compiler for vhdl, but im just using the
schematic input method now as that seems to produce a fit in the small parts
ok.

Ive looked at the IOB on the data sheet and although they have inverted
outputs there is an xor with one input set high or low wich shld enable
selection of active low or active high outputs, both the 16v8 and 22v10 have
inverted outputs with an xor stage and one comes out inverted (q apears as
!q next to the relavent pin on the generated pinout diagram) the other
doesnt, im not sure if I should acount for that in my equations or not. i
think i might be able to figure it out from the jedec file, heck il probaly
end up just writing the jedec file.

Ive looked through the help files however many of the menus/icons I tried to
folow are greyed out wich probably means i need to go and look for more
modules to instal or something. it says something about a constraint editor
but the only option i have is to import a constraint file not edit it.

Colin =^.^=