need small PAL with SR latch

[colin]

Hi,
I need a small prgramable logic device with a couple of SR latches,
however they all seem to have D types or other type of latch on the macro
cell with a global clock/set/reset, exept for some of the realy big ones.

Ive looked through all of the ones that Farnell sell, and although I
could obviously feed back an output to make an SR latch this wouldnt be
ideal, any one know if there are any like this ?

Only needs a dozen gates or so to do the job, could do with being fast
as posible and in circuit programable etc.

Colin =^.^=

 

[Joel Kolstad]

"colin" <no.spam.for.me@ntlworld.com> wrote in message
news:dOVue.4085$BD2.1932@newsfe1-gui.ntli.net...

I need a small prgramable logic device with a couple of SR latches,
however they all seem to have D types or other type of latch on the macro
cell with a global clock/set/reset, exept for some of the realy big ones.
Ive looked through all of the ones that Farnell sell, and although I
could obviously feed back an output to make an SR latch this wouldnt be
ideal, any one know if there are any like this ?

Why do you say that feeding back an output (internally within the part) isn't
ideal? With most of the smaller PLDs, the routing is pretty staightforward
(and fixed!) so it's reasonable to just build your own using the AND-OR array
within the part.

Only needs a dozen gates or so to do the job, could do with being fast
as posible and in circuit programable etc.

I haven't use any non-in-circuit programmable parts in years now; I'm amazed
that anyone still does.

---Joel

 

[Keith Williams]

In article <dOVue.4085$BD2.1932@newsfe1-gui.ntli.net>,
no.spam.for.me@ntlworld.com says...

Hi,
I need a small prgramable logic device with a couple of SR latches,
however they all seem to have D types or other type of latch on the macro
cell with a global clock/set/reset, exept for some of the realy big ones.

Ive looked through all of the ones that Farnell sell, and although I
could obviously feed back an output to make an SR latch this wouldnt be
ideal, any one know if there are any like this ?

Only needs a dozen gates or so to do the job, could do with being fast
as posible and in circuit programable etc.

The Xilinx SpartanXL had RS latch options in the CLBs, but it wasn't
well supported. RS latches tend to cause timing headaches and aren't
recommended. If you insist on RS latches the tools will infer one from
VHDL, though will bitch loudly (at least Synplify would do both).

--
Keith

 

[colin]

"Joel Kolstad" <JKolstad71HatesSpam@yahoo.com> wrote in message
news:11bob0f3t3k37bf@corp.supernews.com...

"colin" <no.spam.for.me@ntlworld.com> wrote in message
news:dOVue.4085$BD2.1932@newsfe1-gui.ntli.net...
I need a small prgramable logic device with a couple of SR latches,
however they all seem to have D types or other type of latch on the
macro
cell with a global clock/set/reset, exept for some of the realy big
ones.
Ive looked through all of the ones that Farnell sell, and although I
could obviously feed back an output to make an SR latch this wouldnt be
ideal, any one know if there are any like this ?

Why do you say that feeding back an output (internally within the part)
isn't
ideal? With most of the smaller PLDs, the routing is pretty
staightforward
(and fixed!) so it's reasonable to just build your own using the AND-OR
array
within the part.

I estimate there would be 6 gates in the circular path as well as the
loading of the output pin and grid lines, compared to a normal latch etc
were there is a circular path of 2 gates with minimal loading. there would
be a significant diference in speed/generated noise. Im trying to acuratly
measure relative edge timings so the faster the better, bit like in a type
II phase detector, except I found that doesnt work quite the way I expected
as it is indeterminate if a waveforem is 90' or 270' out of phase. a simple
xor detector would not alow as much sensitivity.

Only needs a dozen gates or so to do the job, could do with being
fast
as posible and in circuit programable etc.

I haven't use any non-in-circuit programmable parts in years now; I'm
amazed
that anyone still does.

I havent designed in any pld's for ages

Colin =^.^=

 

[Joel Kolstad]

Hi Colin,

"colin" <no.spam.for.me@ntlworld.com> wrote in message
newscXue.4204$BD2.3619@newsfe1-gui.ntli.net...

I estimate there would be 6 gates in the circular path as well as the
loading of the output pin and grid lines, compared to a normal latch etc

Some (possibly even most) parts have the ability to route the AND-OR array
output back to the input side of the array again prior to the output block
(typically this is used when they need to use more product terms than a single
block can provide), and hence the loading of the output pin has essentially
zero effect.

 

[Joerg]

Hello Colin,

I havent designed in any pld's for ages

I have designed out a lot of PLD for ages. Usually because they were
expensive power hogs ;-)

Regards, Joerg

http://www.analogconsultants.com

 

[colin]

"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message
news:io_ue.3500$Bx6.2989@newssvr13.news.prodigy.com...

Hello Colin,

I havent designed in any pld's for ages

I have designed out a lot of PLD for ages. Usually because they were
expensive power hogs ;-)

Regards, Joerg

http://www.analogconsultants.com

what sort of devices did you replace them with ?

Colin =^.^=

 

[Joerg]

Hello Colin,

what sort of devices did you replace them with ?

Mostly with logic. In TSSOP the total real estate usually didn't grow
but the cost was substantially lower. Plus the stuff didn't become
obsolete a few years later.

Sometimes the replacement was a cheap uC, other times a small LUT ROM.

Regards, Joerg

http://www.analogconsultants.com

 

[colin]

"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message
news:uu1ve.3602$Bx6.2241@newssvr13.news.prodigy.com...

Hello Colin,

what sort of devices did you replace them with ?

Mostly with logic. In TSSOP the total real estate usually didn't grow
but the cost was substantially lower. Plus the stuff didn't become
obsolete a few years later.

Sometimes the replacement was a cheap uC, other times a small LUT ROM.

Regards, Joerg

http://www.analogconsultants.com

aha i see,

all i need is 1 nor, 1 nand, 1 sr latch, 2 xor, and a 1 bit tri state
buffer, I could probably do it with a very fast LUT too but im not sure if u
can feedback data lines to address lines reliably unless its clocked,
otherwise thats a few diferent packages even if i try and convert some of
the gates etc.

A gal16v8z doesnt seem to consume much power unless they are hiding it well
in the data sheet, oh wait thats in standby, at 10mhz its 55ma but im not
pumping the clock line so maybe itl be a lot lower.

Colin =^.^=

 

[Joerg]

Hello Colin,

all i need is 1 nor, 1 nand, 1 sr latch, 2 xor, and a 1 bit tri state
buffer, I could probably do it with a very fast LUT too but im not sure if u
can feedback data lines to address lines reliably unless its clocked,
otherwise thats a few diferent packages even if i try and convert some of
the gates etc.

A gal16v8z doesnt seem to consume much power unless they are hiding it well
in the data sheet, oh wait thats in standby, at 10mhz its 55ma but im not
pumping the clock line so maybe itl be a lot lower.

Look at "Normalized Icc versus Freq" in the lattice data sheet on page
19. It doesn't exactly appear to be a static CMOS behavior, there is a
pretty stiff pedestal at 0MHz.

What really irks me and is acutally often the main reason why I do not
use GALs in my designs is the cost. Your 16V8Z, for example, gobbles a
whopping three to four (!) Dollars per chip. No thanks. I can do that
with logic for 50 Cents or so and chances are pretty good that my
clients can buy exactly those same logic chips 15 years from now without
any problems. From half a dozen sources.

Regards, Joerg

http://www.analogconsultants.com

 

[colin]

"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message
news:cyeve.33892$J12.6234@newssvr14.news.prodigy.com...

Hello Colin,

all i need is 1 nor, 1 nand, 1 sr latch, 2 xor, and a 1 bit tri state
buffer, I could probably do it with a very fast LUT too but im not sure
if u
can feedback data lines to address lines reliably unless its clocked,
otherwise thats a few diferent packages even if i try and convert some
of
the gates etc.

A gal16v8z doesnt seem to consume much power unless they are hiding it
well
in the data sheet, oh wait thats in standby, at 10mhz its 55ma but im
not
pumping the clock line so maybe itl be a lot lower.

Look at "Normalized Icc versus Freq" in the lattice data sheet on page
19. It doesn't exactly appear to be a static CMOS behavior, there is a
pretty stiff pedestal at 0MHz.

What really irks me and is acutally often the main reason why I do not
use GALs in my designs is the cost. Your 16V8Z, for example, gobbles a
whopping three to four (!) Dollars per chip. No thanks. I can do that
with logic for 50 Cents or so and chances are pretty good that my
clients can buy exactly those same logic chips 15 years from now without
any problems. From half a dozen sources.

yes there seems to be lots of difernt parts of the same sort, maybe they
would be cheaper otherwise, or if you didnt keep designing them out HA ! the
cheapest I found was 70p @ qty 100

Maybe it has an internal clock running for some reason ? bias generator
perhaps ?

I wonder if the lattice software predicts supply curent im just tryin to get
to grips with that softwar enow.

Colin =^.^=

 

[Joerg]

Hello Colin,

yes there seems to be lots of difernt parts of the same sort, maybe they
would be cheaper otherwise, or if you didnt keep designing them out HA ! the
cheapest I found was 70p @ qty 100

If that is 70 Pence (UK) I'd still consider that expensive.

Maybe it has an internal clock running for some reason ? bias generator
perhaps ?

I wonder if the lattice software predicts supply curent im just tryin to get
to grips with that softwar enow.

Maybe but when something gets warm without doing much I don't like to
design it in.

I was always a bit afraid that someday an assembly house messes up PAL
placement. Others (the PAL aficionados) told me that I am too paranoid
about that. Then came that day. Almost 100 boards totally non-functional
because they had slipped a number on the SMT placement. The boss there
almost went ballistic.

Regards, Joerg

http://www.analogconsultants.com

 

[colin]

"Keith Williams" <krw@att.bizzzz> wrote in message
news:MPG.1d25f957cf413709989ae9@news.individual.net...

In article <dOVue.4085$BD2.1932@newsfe1-gui.ntli.net>,
no.spam.for.me@ntlworld.com says...
Hi,
I need a small prgramable logic device with a couple of SR latches,
however they all seem to have D types or other type of latch on the
macro
cell with a global clock/set/reset, exept for some of the realy big
ones.

Ive looked through all of the ones that Farnell sell, and although I
could obviously feed back an output to make an SR latch this wouldnt be
ideal, any one know if there are any like this ?

Only needs a dozen gates or so to do the job, could do with being
fast
as posible and in circuit programable etc.

The Xilinx SpartanXL had RS latch options in the CLBs, but it wasn't
well supported. RS latches tend to cause timing headaches and aren't
recommended. If you insist on RS latches the tools will infer one from
VHDL, though will bitch loudly (at least Synplify would do both).

--
Keith

thanks,

Im trying to get to grips with some of the software from the manafacturers,
I tried Altera's Quartus II and that seems realy nice and easy to use, and
has no trouble taking my schematic with an rs latch. however they only do
devices many times larger than what i need. with about 100 too many pins!

I tried Lattice and finding this awkward to use but managed to create a
schematic with an rs latch, I was puzzled becuase I couldnt relate this to
the data sheet, however I realise now this isnt what I need as it is using a
D type latch (with a clock wich i had ignored), so I reverted to using 2
gates to do the RS latch function.

Im confused though becuase it seems to have created a gal16v8 but with what
apears on the chip report to be negative logic outputs wich isnt what i
asked for or want.

maybe it would be better to enter it in vhdl ?
what would be an ordinary rs latch as oposed to a equivalent of a clocked D
type latch?

Colin =^.^=

 

[Mike Harrison]

On Sat, 25 Jun 2005 18:16:56 GMT, "colin" <no.spam.for.me@ntlworld.com> wrote:

"Keith Williams" <krw@att.bizzzz> wrote in message
news:MPG.1d25f957cf413709989ae9@news.individual.net...
In article <dOVue.4085$BD2.1932@newsfe1-gui.ntli.net>,
no.spam.for.me@ntlworld.com says...
Hi,
I need a small prgramable logic device with a couple of SR latches,
however they all seem to have D types or other type of latch on the
macro
cell with a global clock/set/reset, exept for some of the realy big
ones.

You can easily do an RS latch in a GAL16V8
in CUPL it would look something like this :

q=q & !reset
# set;

 

[colin]

"Mike Harrison" <mike@whitewing.co.uk> wrote in message
news:9earb1phgmn1bq7ulvb2u2si06n54m342l@4ax.com...

On Sat, 25 Jun 2005 18:16:56 GMT, "colin" <no.spam.for.me@ntlworld.com
wrote:


"Keith Williams" <krw@att.bizzzz> wrote in message
news:MPG.1d25f957cf413709989ae9@news.individual.net...
In article <dOVue.4085$BD2.1932@newsfe1-gui.ntli.net>,
no.spam.for.me@ntlworld.com says...
Hi,
I need a small prgramable logic device with a couple of SR
latches,
however they all seem to have D types or other type of latch on the
macro
cell with a global clock/set/reset, exept for some of the realy big
ones.


You can easily do an RS latch in a GAL16V8
in CUPL it would look something like this :

q=q & !reset
# set;

hi thanks, I managed to get into VHDL and found it reduced my logic a bit
and warned about what apeared to be part of the q node.
so I re wrote my logic to match what was created ...

q <= (a and b) or (a and q) or (b and q);
oe <= a xor b;
ph <= 'Z' when (oe = '0')
else
a xor q;

this time it complained about a node wich was the inverse of q, if i change
my logic to reflect that it goes back to the other node !
so it doesnt seem very predictable. sometimes it seems to generate 2 nodes
wich it warns about, these warned nodes apear on the output pins too.

I also find that on the 16v8 devices my outputs are inverted wich isnt what
i ask for or want, yet on the 22v10 devices it comes out as normal logic.

also im having trouble with the output enable, acodring to the data sheet it
should be able to select 1 line of product terms in complex or simple mode,
but instead of just selecting oe its trying to recalculate oe(a xor b) all
by itself wich it runs out of terms.

Is there an easier way than using lattice software or a more specific user
group ?

Colin =^.^=

 

[John Larkin]

On Fri, 24 Jun 2005 17:15:01 GMT, "colin"
<no.spam.for.me@ntlworld.com> wrote:

"Joel Kolstad" <JKolstad71HatesSpam@yahoo.com> wrote in message
news:11bob0f3t3k37bf@corp.supernews.com...
"colin" <no.spam.for.me@ntlworld.com> wrote in message
news:dOVue.4085$BD2.1932@newsfe1-gui.ntli.net...
I need a small prgramable logic device with a couple of SR latches,
however they all seem to have D types or other type of latch on the
macro
cell with a global clock/set/reset, exept for some of the realy big
ones.
Ive looked through all of the ones that Farnell sell, and although I
could obviously feed back an output to make an SR latch this wouldnt be
ideal, any one know if there are any like this ?

Why do you say that feeding back an output (internally within the part)
isn't
ideal? With most of the smaller PLDs, the routing is pretty
staightforward
(and fixed!) so it's reasonable to just build your own using the AND-OR
array
within the part.

I estimate there would be 6 gates in the circular path as well as the
loading of the output pin and grid lines, compared to a normal latch etc
were there is a circular path of 2 gates with minimal loading. there would
be a significant diference in speed/generated noise. Im trying to acuratly
measure relative edge timings so the faster the better, bit like in a type
II phase detector, except I found that doesnt work quite the way I expected
as it is indeterminate if a waveforem is 90' or 270' out of phase. a simple
xor detector would not alow as much sensitivity.

For a 22v10 sort of architecture, an RS latch is just


Q = Q * \CLR
+ SET

which is just one macrocell.

John

 

[keith]

On Sat, 25 Jun 2005 18:16:56 +0000, colin wrote:

"Keith Williams" <krw@att.bizzzz> wrote in message
news:MPG.1d25f957cf413709989ae9@news.individual.net...
In article <dOVue.4085$BD2.1932@newsfe1-gui.ntli.net>,
no.spam.for.me@ntlworld.com says...
Hi,
I need a small prgramable logic device with a couple of SR latches,
however they all seem to have D types or other type of latch on the
macro
cell with a global clock/set/reset, exept for some of the realy big
ones.

Ive looked through all of the ones that Farnell sell, and although I
could obviously feed back an output to make an SR latch this wouldnt be
ideal, any one know if there are any like this ?

Only needs a dozen gates or so to do the job, could do with being
fast
as posible and in circuit programable etc.

The Xilinx SpartanXL had RS latch options in the CLBs, but it wasn't
well supported. RS latches tend to cause timing headaches and aren't
recommended. If you insist on RS latches the tools will infer one from
VHDL, though will bitch loudly (at least Synplify would do both).

--
Keith

thanks,

Im trying to get to grips with some of the software from the manafacturers,
I tried Altera's Quartus II and that seems realy nice and easy to use, and
has no trouble taking my schematic with an rs latch. however they only do
devices many times larger than what i need. with about 100 too many pins!

Yeow! I have no experience with Altera, but it sounds like you have
something seriously wrong with the setup.

I tried Lattice and finding this awkward to use but managed to create a
schematic with an rs latch, I was puzzled becuase I couldnt relate this
to the data sheet, however I realise now this isnt what I need as it is
using a D type latch (with a clock wich i had ignored), so I reverted to
using 2 gates to do the RS latch function.

The D-flops often have both Sets and Resets, but often they can't be
connected into the routing matrix, or only one can at a time. You are
asking to do something that the manufacturers try to prevent you from
doing. I had similar problems trying to make a D-type latch. While the
two gates should work, the problem is trying to convince the software that
this really is what you want. It will try to prevent you from doing it.

Im confused though becuase it seems to have created a gal16v8 but with
what apears on the chip report to be negative logic outputs wich isnt
what i asked for or want.

I'm confused. You asked for a 16V8, or it chose for you? You may have
IOB issues as well. Getting the IOB right can be a PITA.

maybe it would be better to enter it in vhdl ? what would be an ordinary
rs latch as oposed to a equivalent of a clocked D type latch?

Perhaps something like...
(r,s, and q are standard_logic or standard_ulogic)

SRLatch: Process (S,R) -- Set dominant SR latch
BEGIN
IF s = '1' -- Set is dominant
THEN q <= '1';
ELSE IF r = '1'
THEN q <= '0';
END IF;
END PROCESS;

--
Keith

 

[colin]

"keith" <krw@att.bizzzz> wrote in message
newsan.2005.06.26.16.07.02.195114@att.bizzzz...

On Sat, 25 Jun 2005 18:16:56 +0000, colin wrote:


"Keith Williams" <krw@att.bizzzz> wrote in message
news:MPG.1d25f957cf413709989ae9@news.individual.net...
In article <dOVue.4085$BD2.1932@newsfe1-gui.ntli.net>,
no.spam.for.me@ntlworld.com says...
Hi,
I need a small prgramable logic device with a couple of SR
latches,
however they all seem to have D types or other type of latch on the
macro
cell with a global clock/set/reset, exept for some of the realy big
ones.

Ive looked through all of the ones that Farnell sell, and
although I
could obviously feed back an output to make an SR latch this wouldnt
be
ideal, any one know if there are any like this ?

Only needs a dozen gates or so to do the job, could do with being
fast
as posible and in circuit programable etc.

The Xilinx SpartanXL had RS latch options in the CLBs, but it wasn't
well supported. RS latches tend to cause timing headaches and aren't
recommended. If you insist on RS latches the tools will infer one from
VHDL, though will bitch loudly (at least Synplify would do both).

--
Keith

thanks,

Im trying to get to grips with some of the software from the
manafacturers,
I tried Altera's Quartus II and that seems realy nice and easy to use,
and
has no trouble taking my schematic with an rs latch. however they only
do
devices many times larger than what i need. with about 100 too many
pins!

Yeow! I have no experience with Altera, but it sounds like you have
something seriously wrong with the setup.

I think its just simply that the smaller Altera devices are listed as
'classic' so I gues they dont do them anymore, the software for them 'Max
plus II' is listed as superceded by the new software but that lists the
smallest device as having nearly 100 pins.

I tried Lattice and finding this awkward to use but managed to create a
schematic with an rs latch, I was puzzled becuase I couldnt relate this
to the data sheet, however I realise now this isnt what I need as it is
using a D type latch (with a clock wich i had ignored), so I reverted to
using 2 gates to do the RS latch function.

The D-flops often have both Sets and Resets, but often they can't be
connected into the routing matrix, or only one can at a time. You are
asking to do something that the manufacturers try to prevent you from
doing. I had similar problems trying to make a D-type latch. While the
two gates should work, the problem is trying to convince the software that
this really is what you want. It will try to prevent you from doing it.

Yes I am getting the hint now that they dont want you to do something like
this, I gues they feel clocked logic is more idiot proof, and that were all
idiots or something and timing issues are to hard for us to sort out ... as
it was I now realise the RS latch I thought I had selected was not the
simple type i was after but a clocked version (ie synchrounous set/reset)
and as I had tied the clock to VCC it kindly reduced it to nothing.

Im confused though becuase it seems to have created a gal16v8 but with
what apears on the chip report to be negative logic outputs wich isnt
what i asked for or want.

I'm confused. You asked for a 16V8, or it chose for you? You may have
IOB issues as well. Getting the IOB right can be a PITA.

Confusion abounds ...
The lattice software asks you to select either 16v8,18v8 or 22v10 etc
If I select a gal22v10 it comes out correct but not if I select 16v8,20v8
etc.
Im not sure what i need to do in relation to the IOB for the 16v8 that I
didnt have to with the 22v10 ?
I just let it chose the pin assignments.
I also find that the OE wich can be 1 product term from the matrix is not
able to cope with more terms, even if I asign the equation (a xor b) to
another pin it still tries to use the 2 terms necessary to do the xor rather
then use the term already generated, wich is a bit frustrating. Is there
another software package that would be better than the one lattice provide ?

maybe it would be better to enter it in vhdl ? what would be an ordinary
rs latch as oposed to a equivalent of a clocked D type latch?

Perhaps something like...
(r,s, and q are standard_logic or standard_ulogic)

SRLatch: Process (S,R) -- Set dominant SR latch
BEGIN
IF s = '1' -- Set is dominant
THEN q <= '1';
ELSE IF r = '1'
THEN q <= '0';
END IF;
END PROCESS;

Ah thanks, I was thinking that VHDL would alow you to enter devices from a
library (like you would on a net list) but obviously not.
So the compiler makes sure q doesnt change if s and r are low I gues ? I wil
give it a try
At least now ive got started in VHDL ...

Colin =^.^=

 

[keith]

On Sun, 26 Jun 2005 17:57:43 +0000, colin wrote:

"keith" <krw@att.bizzzz> wrote in message
newsan.2005.06.26.16.07.02.195114@att.bizzzz...
On Sat, 25 Jun 2005 18:16:56 +0000, colin wrote:


"Keith Williams" <krw@att.bizzzz> wrote in message
news:MPG.1d25f957cf413709989ae9@news.individual.net...
In article <dOVue.4085$BD2.1932@newsfe1-gui.ntli.net>,
no.spam.for.me@ntlworld.com says...
Hi,
I need a small prgramable logic device with a couple of SR
latches,
however they all seem to have D types or other type of latch on the
macro
cell with a global clock/set/reset, exept for some of the realy big
ones.

Ive looked through all of the ones that Farnell sell, and
although I
could obviously feed back an output to make an SR latch this wouldnt
be
ideal, any one know if there are any like this ?

Only needs a dozen gates or so to do the job, could do with being
fast
as posible and in circuit programable etc.

The Xilinx SpartanXL had RS latch options in the CLBs, but it wasn't
well supported. RS latches tend to cause timing headaches and aren't
recommended. If you insist on RS latches the tools will infer one from
VHDL, though will bitch loudly (at least Synplify would do both).

--
Keith

thanks,

Im trying to get to grips with some of the software from the
manafacturers,
I tried Altera's Quartus II and that seems realy nice and easy to use,
and
has no trouble taking my schematic with an rs latch. however they only
do
devices many times larger than what i need. with about 100 too many
pins!

Yeow! I have no experience with Altera, but it sounds like you have
something seriously wrong with the setup.

I think its just simply that the smaller Altera devices are listed as
'classic' so I gues they dont do them anymore, the software for them 'Max
plus II' is listed as superceded by the new software but that lists the
smallest device as having nearly 100 pins.

Oh, *now* the light goes on. I thought your design came out with 100
pins. Yes, FPGAs are going to have a lot of pins. ;-)

I tried Lattice and finding this awkward to use but managed to create
a schematic with an rs latch, I was puzzled becuase I couldnt relate
this to the data sheet, however I realise now this isnt what I need
as it is using a D type latch (with a clock wich i had ignored), so I
reverted to using 2 gates to do the RS latch function.

The D-flops often have both Sets and Resets, but often they can't be
connected into the routing matrix, or only one can at a time. You are
asking to do something that the manufacturers try to prevent you from
doing. I had similar problems trying to make a D-type latch. While
the two gates should work, the problem is trying to convince the
software that this really is what you want. It will try to prevent you
from doing it.

Yes I am getting the hint now that they dont want you to do something
like this, I gues they feel clocked logic is more idiot proof, and that
were all idiots or something and timing issues are to hard for us to
sort out ... as it was I now realise the RS latch I thought I had
selected was not the simple type i was after but a clocked version (ie
synchrounous set/reset) and as I had tied the clock to VCC it kindly
reduced it to nothing.

Not necessarily more idiot-proof, but clocked logic can be simulated
and timed. Asynchronous logic and loops in logic are nightmares.

Im confused though becuase it seems to have created a gal16v8 but
with what apears on the chip report to be negative logic outputs wich
isnt what i asked for or want.

I'm confused. You asked for a 16V8, or it chose for you? You may have
IOB issues as well. Getting the IOB right can be a PITA.

Confusion abounds ...

;-)

The lattice software asks you to select either 16v8,18v8 or 22v10 etc If
I select a gal22v10 it comes out correct but not if I select 16v8,20v8
etc.
Im not sure what i need to do in relation to the IOB for the 16v8 that I
didnt have to with the 22v10 ?
I just let it chose the pin assignments. I also find that the OE wich
can be 1 product term from the matrix is not able to cope with more
terms, even if I asign the equation (a xor b) to another pin it still
tries to use the 2 terms necessary to do the xor rather then use the
term already generated, wich is a bit frustrating. Is there another
software package that would be better than the one lattice provide ?

maybe it would be better to enter it in vhdl ? what would be an
ordinary rs latch as oposed to a equivalent of a clocked D type
latch?

Perhaps something like...
(r,s, and q are standard_logic or standard_ulogic)

SRLatch: Process (S,R) -- Set dominant SR latch
BEGIN
IF s = '1' -- Set is dominant
THEN q <= '1';
ELSE IF r = '1'
THEN q <= '0';
END IF;
END PROCESS;


Ah thanks, I was thinking that VHDL would alow you to enter devices from
a library (like you would on a net list) but obviously not.

It will. You can instantiate devices directly, much like a text version
of a schematic. You need to know what is in the library though. I try not
to do this because it messes up the VHDL and makes it less portable. When
I find it necessary, I keep all such instantiations in seperate files and
mark them as being technology dependent.

So the
compiler makes sure q doesnt change if s and r are low I gues ? I wil
give it a try

If R and S are low, neither IF clause is triggered and the data is
whatever it was. If either is active that clause is triggered and the
appropriate THEN is executed. One key point here is the sensitivity list
in the process statement "(s,r)". This triggers the process to be
evaluated whenever R or S changes state.

At least now ive got started in VHDL ...

I found VHDL, at least the synthesizable subset, to be very easy to learn.
Much of the difficulty is in knowing what synghesis is going to do with
your source code. Synthesis matches templates, so your job, should you
choose to accept, ;-) is to learn what templates turn out what logic.

--
Keith

 

[colin]

"keith" <krw@att.bizzzz> wrote in message
newsan.2005.06.26.18.14.06.823026@att.bizzzz...

<big snip >

Oh, *now* the light goes on. I thought your design came out with 100
pins. Yes, FPGAs are going to have a lot of pins. ;-)

Its amasing just how many pins some of theses devices have, and with oudles
of gates too and 400mhz clock speed etc, and yet they stil dont consume that
much more power than some of the small ones.

Im realy tempted to try and do something neat to do with all those pins but
cant think of anything right now.

Not necessarily more idiot-proof, but clocked logic can be simulated
and timed. Asynchronous logic and loops in logic are nightmares.

Yes its easy to verify setup times are met with clocked logic as everything
just adds up between the edges.

Metastable states in asynch loops can cuase nightmares but they still have
defineable boundries, the latches in the macro cells have internal async
loops hence the setup and min clock width timings inorder to avoid
metastable states but it is much more controled as they will only have 2
adjacent virtualy unloaded gates in the loop.

In logic wich has numerous feedback loops all the possible circular paths
can be very complex and hard to ensure metastable (or race conditon) states
are avoided, but as the theory is reasonably simple a computer should be
able to handle the complexity, but it seems the tools are made to do it the
easy way.

However it seems high speed clocks accross large chips are cuasing problems
and theres interest in using more asycnhrounous techniques such as mixed non
synchronised clock systems however these seem to cuase as much problems, if
you could make a microprocessor internaly completly asynchronous (with of
course suitablly generated handshaking for every movement of data) it would
avoid clock issues altogether.

You need to know what is in the library though. I try not
to do this because it messes up the VHDL and makes it less portable. When
I find it necessary, I keep all such instantiations in seperate files and
mark them as being technology dependent.

ah yes of course, il have a look to see if there are any asycnhrounous sr
latches already there.

I found VHDL, at least the synthesizable subset, to be very easy to learn.
Much of the difficulty is in knowing what synghesis is going to do with
your source code. Synthesis matches templates, so your job, should you
choose to accept, ;-) is to learn what templates turn out what logic.

That reminds me of trying to use high level languages in multi tasking
embeded systems.

Colin =^.^=